KS8695X View Datasheet(PDF) - Micrel
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Description
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KS8695X Datasheet PDF : 39 Pages
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Micrel, Inc.
KS8695X
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O) (continued)
Pin
Name
I/O Type(1) Description
78
EWAITN
I
External wait: Active low. This signal is asserted when an external I/O device or a
ROM/SRAM/FLASH bank needs more access cycles than those defined in the
corresponding control register.
81
RCSN[1]
82
RCSN[0]
O
ROM/SRAM/FLASH chip select: Active low. The KS8695X can access up to two
external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
map the CPU addresses into physical memory banks.
85
EROEN/
WRSTPLS
O/I
Normal mode: External I/O and ROM/SRAM/FLASH output enable:Active low.
When asserted, this signal controls the output enable port of the specified memory
device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active low;
WRSTPLS = 1, active high. No default.
89
ERWEN0/
TESTACK
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory test signal).
88
ERWEN1/
TESTREQB
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory test signal).
87
ERWEN2/
TESTREQA
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device except SDRAM).
ARM CPU test signal (factory test signal).
86
ERWEN3/
TICTESTENN
O
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory test signal).
119
WLED0/
B0SIZE0
O/I
Normal mode: WAN LED indicator 0:Programmable via WAN misc. Control register
bits [2:0].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
118
WLED1/
B0SIZE1
O/I
Normal mode: WAN LED indicator 1:Programmable via WAN Misc. Control register
bits [6:4].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
Factory Test Pins
Pin
Name
I/O Type(1) Description
117
TESTEN
I
Chip test enable: (factory test signal), pull down if not used.
197
TEST1
I
PHY test pin: (factory test signal).
149
TEST2
I
PHY test pin: (factory test signal).
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
June 2006
23
M9999-060106
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