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KM416C1204C-45 View Datasheet(PDF) - Samsung

Part NameDescriptionManufacturer
KM416C1204C-45 1M x 16Bit CMOS Dynamic RAM with Extended Data Out Samsung
Samsung Samsung
KM416C1204C-45 Datasheet PDF : 35 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
KM416C1004C, KM416C1204C
KM416V1004C, KM416V1204C
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K
Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsungs advanced CMOS process to
realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal
computer and portable machines.
FEATURES
Part Identification
- KM416C1004C/C-L (5V, 4K Ref.)
- KM416C1204C/C-L (5V, 1K Ref.)
- KM416V1004C/C-L (3.3V, 4K Ref.)
- KM416V1204C/C-L (3.3V, 1K Ref.)
Active Power Dissipation
Speed
-45
-5
-6
3.3V
4K
1K
-
-
324
504
288
468
Unit : mW
5V
4K
1K
550
825
495
770
440
715
Refresh Cycles
Part
NO.
C1004C
V1004C
C1204C
V1204C
VCC Refresh
cycle
5V
4K
3.3V
5V
1K
3.3V
Refresh period
Normal L-ver
64ms
16ms
128ms
Performance Range
Speed
-45
-5
-6
tRAC
45ns
50ns
60ns
tCAC
13ns
15ns
17ns
tRC
69ns
84ns
104ns
tHPC
16ns
20ns
25ns
Remark
5V/3.3V
5V/3.3V
5V/3.3V
• Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in plastic SOJ 400mil and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
UCAS
LCAS
W
Control
Clocks
VBB Generator
A0-A11
(A0 - A9) *1
A0 - A7
(A0 - A9) *1
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
1,048,576 x16
Cells
Column Decoder
Note) *1 : 1K Refresh
Vcc
Vss
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
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