|KM416V1204C||1M x 16Bit CMOS Dynamic RAM with Extended Data Out|
|KM416V1204C Datasheet PDF : 35 Pages |
11. tASC, tCAH are referenced to the earlier CAS falling edge.
12. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
13. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
14. tCWL is specified from W falling edge to the earlier CAS rising edge.
15. tCSR is referenced to the earlier CAS falling edge before RAS transition low.
16. tCHR is referenced to the later CAS rising edge after RAS transition low.
17. tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
18. tASC≥6ns, assume tT=2.0ns.
19. If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
20. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
22. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
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