datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

K9F2G08R0A View Datasheet(PDF) - Samsung

Part Name
Description
View to exact match
K9F2G08R0A Datasheet PDF : 44 Pages
First Prev 41 42 43 44
K9F2G08R0A
K9F2G08U0A
FLASH MEMORY
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.
Figure 18. Read ID Operation
CLE
CE
tCLR
tCEA
WE
ALE
RE
tAR
tWHR
I/OX
90h
00h
Address. 1cycle
tREA
ECh
Maker code
Device
Code
3rd Cyc.
Device code
4th Cyc. 5th Cyc.
Device
K9F2G08R0A
K9F2G08U0A
Device Code (2nd Cycle)
AAh
DAh
3rd Cycle
00h
10h
4th Cycle
15h
95h
5th Cycle
44h
44h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 19
below.
Figure 19. RESET Operation
tRST
R/B
I/OX
FFh
Table 5. Device Status
Operation mode
After Power-up
00h Command is latched
After Reset
Waiting for next command
42
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]