KM416L8031BT-GLY View Datasheet(PDF) - Samsung
Part Name
Description
View to exact match
KM416L8031BT-GLY Datasheet PDF : 53 Pages
| |||
128Mb DDR SDRAM
8Mx16
Symbol
K4H281638B-TCA2
(DDR266A)
K4H281638B-TCB0
(DDR266B)
K4H281638B-TCA0
(DDR200)
Unit
Notes
typical worst
typical worst
typical worst
IDD0
90
95
90
95
80
85
mA
IDD1
140
155
140
155
135
150
mA
IDD2P
21
25
21
25
20
24
mA
IDD2F
40
45
40
45
35
40
mA
IDD2Q
30
35
30
35
27
32
mA
IDD3P
25
30
25
30
20
25
mA
IDD3N
45
50
45
50
35
40
mA
IDD4R
210
245
210
245
155
175
mA
IDD4W
150
165
150
165
110
125
mA
IDD5
195
210
195
210
180
190
mA
IDD6
Normal
2
2
2
2
2
2
mA
Low power
1
1
1
1
1
1
mA
Optional
IDD7
300
340
300
340
275
300
mA
Table 12. 128Mb DDR SDRAM IDD SPEC Table
< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
- 42 -
REV. 1.0 November. 2. 2000
|
|
Share Link: 