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KM416L8031BT-GL0 View Datasheet(PDF) - Samsung

Part NameDescriptionManufacturer
KM416L8031BT-GL0 128Mb DDR SDRAM Samsung
Samsung Samsung
KM416L8031BT-GL0 Datasheet PDF : 53 Pages
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128Mb DDR SDRAM
3.2.2.2 Extended Mode Register Set(EMRS)
The extended mode register stores the data for enabling or disabling DLL, QFC and selecting output driver
size. The default value of the extended mode register is not defined, therefore the extened mode register must
be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low
on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the
same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Two clock cycles
are required to complete the write operation in the extended mode register. The mode register contents can
be changed using the same command and clock cycle requirements during operation as long as all banks are
in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
RFU 1
RFU : Must be set "0"
QFC D.I.C DLL Extended Mode Register
BA0
An ~ A0
0
(Existing)MRS Cycle
1
Extended Funtions(EMRS)
Output Driver Impedence Control
0
Normal
1
Weak
A0 DLL Enable
0
Enable
1
Disable
QFC control
0
Disable(Default)
1
Enable
Figure 7. Extend Mode Register set
- 17 -
REV. 1.0 November. 2. 2000
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