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KM416L8031BT-GL0 View Datasheet(PDF) - Samsung

Part NameDescriptionManufacturer
KM416L8031BT-GL0 128Mb DDR SDRAM Samsung
Samsung Samsung
KM416L8031BT-GL0 Datasheet PDF : 53 Pages
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128Mb DDR SDRAM
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make
DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined,
therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode
register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank pre-
charge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in
the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles
are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. The mode register is divided into various fields depending on functionality. The burst length uses
A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used
for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for
specific codes for various burst lengths, addressing modes and CAS latencies.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
RFU 0
RFU
DLL TM CAS Latency BT Burst Length Mode Register
A8 DLL Reset A7
mode
A3 Burst Type
0
No
0 Normal
0 Sequential
1
Yes
1
Test
1 Interleave
Burst Length
CAS Latency
A6 A5 A4 Latency
A2 A1 A0
BA0
An ~ A0
0
(Existing)MRS Cycle
1 Extended Funtions(EMRS)
0 0 0 Reserved
0 0 1 Reserved
010
2
0 1 1 Reserved
000
001
010
011
1 0 0 Reserved
100
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
1 0 1 Reserved
110
2.5
1 1 1 Reserved
101
110
111
Latency
Sequential Interleave
Reserve
Reserve
2
2
4
4
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Figure 5. Mode Register Set
- 15 -
REV. 1.0 November. 2. 2000
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