datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

KM416L8031BT-GL0 View Datasheet(PDF) - Samsung

Part NameDescriptionManufacturer
KM416L8031BT-GL0 128Mb DDR SDRAM Samsung
Samsung Samsung
KM416L8031BT-GL0 Datasheet PDF : 53 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
128Mb DDR SDRAM
2.2 Input/Output Function Description
SYMBOL
CK, CK
CKE
CS
RAS, CAS, WE
LDM,(U)DM
BA0, BA1
A [n : 0]
DQ
LDQS,(U)DQS
QFC
NC
VDDQ
VSSQ
VDD
VSS
VREF
TYPE
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
Output
-
Supply
Supply
Supply
Supply
Input
DESCRIPTION
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled
during power-down and self refresh modes, providing low standby power. CKE will recognize
an LVCMOS LOW level prior to VREF being stable on power-up.
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-
ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on
DQ8-DQ15.
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address
inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1
define which mode register is loaded during the MODE REGISTER SET command (MRS or
EMRS).
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.
FET Control : Optional. Output during every Read and Write access. Can be used to control
isolation switches on modules.
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.5V ± 0.2V.
DQ Ground.
Power Supply : +2.5V ± 0.2V (device specific).
Ground.
SSTL_2 reference voltage.
Table 3. Input/Output Function Description
- 11 -
REV. 1.0 November. 2. 2000
Direct download click here
 

Share Link : Samsung
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]