ISL97635A View Datasheet(PDF) - Intersil

Part Name

Description

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ISL97635A

SMBus 6-Channel LED Driver

Intersil 

ISL97635A

Electrical Specifications

All specifications below are tested at TA = -40°C to +85°C; VIN = 12V, EN = 5V, RSET = 36.6kΩ, unless

otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise

specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER

DESCRIPTION

CONDITION

MIN TYP MAX UNIT

Eff_peak

Peak Efficiency

ΔIOUT/ΔVIN

Dmax

Dmin

FOSC_hi

FOSC_lo

ILX_leakage

Line Regulation

Boost Maximum Duty Cycle

Boost Minimum Duty Cycle

LX Frequency

LX Frequency

LX Leakage Current

VIN = 18V, 54 LEDs, 20mA each, L = 8.2µH

91

%

with DCR 106mΩ, TA = +25°C

VIN = 12V, 54 LEDs, 20mA each, L = 8.2µH

88

%

with DCR 106mΩ, TA = +25°C

VIN = 6V, 54 LEDs, 20mA each, L = 8.2µH

86

%

with DCR 106mΩ, TA = +25°C

0.1

%

82

%

7

%

Register 0x08, fSW = 1

Register 0x08, fSW = 0

VLX = 36V, EN = 0

1.0 1.2 1.3 MHz

550 600 650 kHz

10 µA

REFERENCE

IMATCH

Channel-to-Channel Current Matching

IACC

Current Accuracy

FAULT DETECTION

IOUT = 30mA, BRT = 255

-3.5 ±1 +3.5 %

±3

%

VSC

Short Circuit Threshold

Reg0x08 = 0x0F or 0x0B Reg0x00 = 0xFF 7.8 8 8.8 V

Reg0x08 = 0x0E or 0x0A Reg0x00 = 0xFF 2.8 3.1 3.8 V

Vtemp_acc

Over-Temperature Threshold Accuracy

VOVPlo

Overvoltage Limit on OVP Pin

OVPhys

OVP Hysteresis

OVPfault

OVP Short Detection Fault Level

SMBus INTERFACE

5

°C

1.17 1.2 1.23 V

20

mV

300

mV

VIL

Guaranteed Range for Data, Clock Input Low

Voltage

0.8 V

VIH

Guaranteed Range for Data, Clock Input High

Voltage

2.1

VDD V

VOL

SMBus Data Line Logic Low Voltage with 1.1kΩ

Series Resistor from Data Bus to SMBDAT pin

IPULLUP = 350µA

0.4 V

SMBus Data Line Logic Low Voltage without Series IPULLUP = 4mA

Resistor from Data Bus to SMBDAT Pin

0.17 V

ILEAK

Input Leakage on SMBData/SMBClk

VDD

Nominal Bus Voltage

SMBus TIMING SPECIFICATIONS (Note 4)

3V to 5V ±10%

-1

1 µA

2.7

5.5 V

fSMB

tBUF

tHD:STA

SMBus Clock Frequency

Bus Free Time between STOP and START Condition

Hold Time after (Repeated) START Condition. After

this Period, the First Clock is Generated.

10

100 kHz

4.7

µs

4.0

µs

tSU:STA

tSU:STO

tHD:DAT

Repeated Start Condition Setup Time

Stop Condition Setup Time

Data Hold Time

4.7

µs

4.0

µs

300

ns

5

FN6564.2

December 22, 2008

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