ISL95820 View Datasheet(PDF) - Intersil
Part Name
Description
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ISL95820 Datasheet PDF : 47 Pages
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ISL95820
Pin Descriptions
PIN #
BOTTOM
PAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16
17
18
19
20
21
22
23
24
25
SYMBOL
DESCRIPTION
GND
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pad. It should also be used as the
thermal pad for heat removal.
VR_ON Controller enable input. A high level logic signal on this pin enables the controller.
PGOOD
Power-Good open-drain output indicating when VR is able to supply regulated voltage. Pull-up externally to VDD or to a
lower supply, such as 3.3V.
IMON
VR output current monitor. IMON sources a current proportional to the regulator output current. A resistor to ground
determines the scaling of the IMON voltage to output current.
VR_HOT# Open drain thermal overload output indicator. Part of the communication bus with the CPU.
NTC
The thermistor input to VR_HOT# circuit. Use it to monitor VR temperature.
COMP This pin is the output of the VR error amplifier. It provides error amplifier feedback to the compensation network.
FB
This pin is the inverting input of the VR error amplifier. A DAC-derived voltage equal to the VID reference voltage is
connected internally to the non-inverting error amplifier input.
FB2
There is an internal switch between FB pin and FB2 pin. The switch is off (open) when VR is in 1-phase mode and is on
(closed) otherwise. The components connecting to FB2 are used to adjust the compensation in 1-phase mode to achieve
optimum performance for VR.
FB3
There is an internal switch between pins FB and FB3. The switch will be on (closed) in droop mode (whenever
programmable output DC loadline operation is enabled), and off (open) when no-droop mode is selected. The purpose is
to include a resistor in parallel with the fixed droop resistor when droop is active, and to isolate that resistor when droop
is inactive. This parallel resistor increases the open-loop gain of the compensator while droop is active. The effective
droop (output DC loadline) programming resistance is the parallel combination of these two resistors.
ISEN4
Individual current sensing for Phase4. When ISEN4 is pulled to VDD (5V), the controller will disable VR Phase 4. This
signal is used to monitor for and to correct phase current imbalance.
ISEN3
Individual current sensing for Phase3. When ISEN4 and ISEN3 is pulled to VDD (5V), the controller will disable VR Phases
4 and 3. Do not disable Phase 3 without also disabling Phase 4. This signal is used to monitor for and to correct phase
current imbalance.
ISEN2
Individual current sensing for Phase 2. When ISEN4, ISEN3 and ISEN2 are pulled to VDD (5V), the controller will disable
VR Phases 4, 3 and 2. Do not disable Phase 2 without also disabling Phases 3 and 4. This signal is used to monitor for
and to correct phase current imbalance.
ISEN1 Individual current sensing for Phase 1. This signal is used to monitor for and to correct phase current imbalance.
RTN
Remote ground (return) voltage sensing. Part of the differential remote VR voltage sense network.
ISUMN and VR droop current sensing inputs.
ISUMP
VDD
+5V bias power.
BOOT1
Phase 1 internal gate driver high-side MOSFET bootstrap capacitor connection. Connect an MLCC capacitor between the
BOOT1 and the PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin
to the BOOT1 pin each time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot diode.
PHASE1
Current return path for Phase 1 high-side MOSFET gate driver. Connect the PHASE1 pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase1.
UGATE1 Output of Phase 1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of Phase 1 high-side MOSFET.
LGATE1 Output of Phase 1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of Phase 1 low-side MOSFET.
BOOT2
Phase 2 internal gate driver high-side MOSFET bootstrap capacitor connection. Connect an MLCC capacitor between the
BOOT2 and the PHASE2 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin
to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot diode.
PHASE2
Current return path for Phase 2 high-side MOSFET gate driver. Connect the PHASE2 pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2.
UGATE2 Output of Phase 2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of Phase 2 high-side MOSFET.
VCCP
Input voltage bias for the internal gate drivers. Connect +5V or +12V to the VCCP pin. Decouple with at least 1µF of an
MLCC capacitor. Diode Emulation Mode must be disabled (using PROG2 pin resistor) for +5V driver operation.
4
FN8318.0
February 4, 2013
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