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ISL8483ECPZ View Datasheet(PDF) - Intersil

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Description
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ISL8483ECPZ Datasheet PDF : 14 Pages
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ISL8483E, ISL8485E
Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = +25°C, (Note 2) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP MIN
MAX
(°C) (Note 12) TYP (Note 12) UNITS
No-Load Supply Current, (Note 3)
ICC ISL8485E, DI, RE = 0V or VCC DE = VCC
Full
-
700
900
µA
DE = 0V
Full
-
500
565
µA
ISL8483E, DI, RE = 0V or VCC DE = VCC
Full
-
470
650
µA
DE = 0V
Full
-
160
250
µA
Shutdown Supply Current
ISHDN ISL8483E, DE = 0V, RE = VCC, DI = 0V or VCC Full
-
Driver Short-Circuit Current,
VO = High or Low
IOSD1 DE = VCC, -7V VY or VZ 12V, (Note 4)
Full
35
Receiver Short-Circuit Current
IOSR 0V VO VCC
Full
7
SWITCHING CHARACTERISTICS (ISL8485E)
1
50
nA
-
250
mA
-
85
mA
Driver Input to Output Delay
tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Output Skew
tSKEW RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure 2)
Driver Enable to Output High
tZH CL = 100pF, SW = GND, (Figure 3)
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3)
Driver Disable from Output High
tHZ CL = 15pF, SW = GND, (Figure 3)
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Receiver Input to Output Delay
tPLH, tPHL (Figure 4)
Receiver Skew | tPLH - tPHL |
tSKD (Figure 4)
Receiver Enable to Output High
tZH CL = 15pF, SW = GND, (Figure 5)
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5)
Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure 5)
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Maximum Data Rate
fMAX (Note 11)
SWITCHING CHARACTERISTICS (ISL8483E)
Full
18
Full
-
Full
3
Full
-
Full
-
Full
-
Full
-
Full
30
25
-
Full
-
Full
-
Full
-
Full
-
Full
10
30
50
ns
2
10
ns
11
25
ns
17
70
ns
14
70
ns
19
70
ns
13
70
ns
40
150
ns
5
-
ns
9
50
ns
9
50
ns
9
50
ns
9
50
ns
-
-
Mbps
Driver Input to Output Delay
tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
250
800 2000
ns
Driver Output Skew
tSKEW RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
-
160
800
ns
Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
250
800 2000
ns
Driver Enable to Output High
tZH CL = 100pF, SW = GND, (Figure 3), (Note 5) Full
250
-
2000
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3), (Note 5)
Full
250
-
2000
ns
Driver Disable from Output High
tHZ CL = 15pF, SW = GND, (Figure 3)
Full
300
-
3000
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
300
-
3000
ns
Receiver Input to Output Delay
tPLH, tPHL (Figure 4)
Full
250
350 2000
ns
Receiver Skew | tPLH - tPHL |
tSKD (Figure 4)
25
-
25
-
ns
Receiver Enable to Output High
tZH CL = 15pF, SW = GND, (Figure 5), (Note 6)
Full
-
10
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5), (Note 6)
Full
-
10
50
ns
Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure 5)
Full
-
10
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
10
50
ns
Maximum Data Rate
fMAX (Note 11)
Full
250
-
-
kbps
Time to Shutdown
tSHDN (Note 7)
Full
50
200
600
ns
Driver Enable from Shutdown to tZH(SHDN) CL = 100pF, SW = GND, (Figure 3), (Notes 7, 8) Full
-
Output High
-
2000
ns
5
FN6048.9
September 9, 2008
 

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