ISL8200M_10 View Datasheet(PDF) - Intersil

Part Name

Description

View to exact match

ISL8200M_10

Complete Current Share 10A DC/DC Power Module

Intersil 

ISL8200M

Pin Descriptions (Continued)

PIN

NUMBER PIN NAME

PIN DESCRIPTION

21

VCC

Analog Input - This pin provides bias power for the analog circuitry. It’s operational range is 2.97V to

5.6V. In 3.3V applications, VCC, PVCC and VIN should be shorted to allow operation at the low end

input as it relates to the VCC falling threshold limit. This pin can be powered either by the internal linear

regulator or by an external voltage source.

22

PGOOD Analog Output - Provides an open drain Power Good signal when the output is within 9% of nominal

output regulation point with 4% hysteresis (13%/9%), and soft-start is complete. PGOOD monitors the

outputs (VMON1) of the internal differential amplifiers. Output Voltage Range: 0V to VCC.

23

NC

Not internal connected

PD1

Phase Used for both the PHASE pin (Pin # 16) and for heat removal connecting to heat dissipation layers using

Thermal Pad Vias. Potential should be floating and not electrically connected to anything except PHASE pin 16.

PD2

VIN Thermal Used for both the PVIN pin (Pin # 17) and for heat removal connecting to heat dissipation layers using

Pad

Vias. Potential should be floating and not electrically connected to anything except VPVIN pin 17.

PD3

PGND Used for both the PGND pin (Pin # 18) and for heat removal connecting to heat dissipation layers using

Thermal Pad Vias. Potential should be floating and not electrically connected to anything except PGND pin 18.

PD4

VOUT

Used for both the VOUT pin (Pin # 19) and for heat removal connecting to heat dissipation layers using

Thermal Pad Vias. Potential should be floating and not electrically connected to anything except VOUT pin 19.

Typical Application Circuits

VIN

GND

U201

I SL 8200 M

R1

16. 5k

C IN (C ER )

PVIN

VI N

R2

4. 12k

CEN

1nF

* Select R1 & R2

such that

0.8V<VEN<5.0V

FF

EN

ISF ETDRV1

FS Y N C _I N

CL KOU T

ISH AR E_ BU S

ISFE TD R V

VOU T

VOUT

GND

2.2k

R S ET

C OU T

V OU T_ SE T

V SEN _R EM-

PGOOD 1

PGOOD

P H _C N TR L

VC C

(See Table 1,

VOUT - RSET on page 13)

R I SH AR E

5k

C PV CC

10uF

FIGURE 3. SINGLE PHASE 10A 1.2V OUTPUT CIRCUIT

5

FN6727.1

February 26, 2010

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