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5962R0922503V9A View Datasheet(PDF) - Intersil

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5962R0922503V9A Datasheet PDF : 25 Pages
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ISL70001ASEH
because that is the lower limit of the current limit threshold with
all six power blocks connected.
13
12
11
10
9
8
7
6
5
4
120
12.14
10.18
8.57
MINIMUM OCP
LEVEL = 7.8A
7.25
6.16
6A @ +146°C
5.3
125 130 135 140 145 150 155
JUNCTION TEMPERATURE (°C)
FIGURE 26. CURRENT vs TEMPERATURE
PCB Design
PCB design is critical to high-frequency switching regulator
performance. Careful component placement and trace routing
are necessary to reduce voltage spikes and minimize
undesirable voltage drops. Selection of a suitable thermal
interface material is also required for optimum heat dissipation
and to provide lead strain relief. See Table 1 on page 21 for
layout x-y coordinates.
PCB Plane Allocation
Four layers of 2-ounce copper are recommended. Layer 2 should
be a dedicated ground plane with all critical component ground
connections made with vias to this layer. Layer 3 should be a
dedicated power plane split between the input and output power
rails. Layers 1 and 4 should be used primarily for signals but can
also provide additional power and ground islands, as required.
PCB Component Placement
Components should be placed as close as possible to the IC to
minimize stray inductance and resistance. Prioritize the
placement of bypass capacitors on the pins of the IC in the order
shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors),
EN, PGOOD, PVINx (bulk capacitors).
Locate the output voltage resistive divider as close as possible to
the FB pin of the IC. The top leg of the divider should connect
directly to the POL (Point of Load), and the bottom leg of the
divider should connect directly to AGND. The junction of the
resistive divider should connect directly to the FB pin.
Locate a Schottky clamp diode as close as possible to the LXx
and PGNDx pins of the IC. A small series R-C snubber connected
from the LXx pins to the PGNDx pins may be used to damp high
frequency ringing on the LXx pins, if desired, see Figure 27.
ERROR
AMPLIFIER
-
+ VREF
LXx
LOUT
3A
RS
CS
PGNDx
FB
REF
CREF
COUT
VOUT
RT CC
RB
FIGURE 27. SCHOTTKY DIODE AND R-C SNUBBER
PCB Layout
Use a small island of copper to connect the LXx pins of the IC to
the output inductor on Layers 1 and 4. To minimize capacitive
coupling to the power and ground planes, void the copper on
Layers 2 and 3 adjacent to the island. Place most of the island of
Layer 4 to minimize the amount of copper that must be voided
from the ground plane (Layer 2).
Keep all other signal traces as short as possible.
For an example layout, see AN1842.
Thermal Management for Ceramic Package
For optimum thermal performance, place a pattern of vias and a
thermal land on the top layer of the PCB directly underneath the
IC. Connect the vias to the plane which serves as a heat sink. To
ensure good thermal contact, thermal interface material such as
a Sil-Pad or thermally conductive epoxy should be used to fill the
gap between the vias and the bottom of the ceramic package.
Lead Strain Relief
The package leads protrude from the bottom of the package and
the leads need forming to provide strain relief. On the ceramic
bottom package R48.A, the Sil-pad or epoxy maybe be used to fill
the gap left between the PCB board and the bottom of the
package when lead forming is completed. On the heat sink
option of the package, R48.B, the lead forming should be made
so that the bottom of the heat sink and the formed leads are
flush.
Heat Sink Mounting Guidelines
The R48.B package option has a heat sink mounted on the
underside of the package. The following JESD51-5 guidelines
may be used to mount the package:
1. Place a thermal land on the PCB under the heat sink.
2. The land should be approximately the same size as to 1mm
larger than the 9x9mm heat sink.
18
FN8365.0
May 22, 2013
 

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