5962R0922503V9A View Datasheet(PDF) - Intersil
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5962R0922503V9A Datasheet PDF : 25 Pages
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ISL70001ASEH
Due to the current loop feedback in peak current mode control, the
modulator has a single pole response with -20dB slope at a
frequency determined by the load (Equation 8):
FPO = -2----π----⋅---R----O-1----⋅---C----O----U---T-
(EQ. 8)
where RO is load resistance and COUT is the output load
capacitance. For this type of modulator, a Type 2 compensation
circuit is usually sufficient.
Figure 25 shows a Type 2 amplifier and its response, along with
the responses of the current mode modulator and the converter.
C2
CONVERTER
R2 C1
R1
EA
TYPE 2 EA
MODULATOR
FPO
GEA = 25.1dB
FZ
FP
FC
FIGURE 25. FEEDBACK LOOP COMPENSATION
The Type 2 amplifier, in addition to the pole at origin, has a
zero-pole pair that causes a flat gain region at frequencies
between the zero and the pole (Equations 9 and 10).
FZ
=
--------------1---------------
2π ⋅ R2 ⋅ C1
=
8.6 k H z
(EQ. 9)
FP = 2----π-----⋅---R--1--1-----⋅---C----2- = 546kHz
(EQ. 10)
Zero frequency and amplifier high-frequency gain were chosen to
satisfy typical applications. The crossover frequency will appear
at the point where the modulator attenuation equals the
amplifier high frequency gain. The only task that the system
designer has to complete is to specify the output filter capacitors
to position the load main pole somewhere within one decade
lower than the amplifier zero frequency. Equation 13 on page 17
approximates the amount of capacitance needed to achieve an
optimal pole location depending on the number of LXx pins
connected. With this type of compensation, plenty of phase
margin is easily achieved due to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole is
positioned too much to the left side on the frequency axis due to
excessive output filter capacitance. In this case, the ESR zero
placed within the 1.2kHz to 30kHz range gives some additional
phase ‘boost’. Some phase boost is also achieved by connecting
the recommended capacitor CC in parallel with the upper resistor
RT of the divider that sets the output voltage value, as
demonstrated in Figure 22.
Component Selection Guide
This design guide is intended to provide a high-level explanation
of the steps necessary to create a power converter. It is assumed
the reader is familiar with many of the basic skills and
techniques referenced below. In addition to this guide, Intersil
provides a complete evaluation board that includes schematic,
BOM, and an example PCB layout (see Ordering Information
table on page 2).
Output Filter Design
The output inductor and the output capacitor bank together form
a low-pass filter responsible for smoothing the pulsating voltage
at the phase node. The filter must also provide the transient
energy until the regulator can respond. Since the filter has low
bandwidth relative to the switching frequency, it limits the
system transient response. The output capacitors must supply or
sink current while the current in the output inductor increases or
decreases to meet the load demand.
OUTPUT CAPACITOR SELECTION
The critical load parameters in choosing the output capacitors are
the maximum size of the load step (ΔISTEP), the load-current slew
rate (di/dt), and the maximum allowable output voltage deviation
under transient loading (ΔVMAX). Capacitors are characterized
according to their capacitance, ESR (Equivalent Series Resistance)
and ESL (Equivalent Series Inductance).
At the beginning of a load transient, the output capacitors supply all
of the transient current. The output voltage initially deviates by an
amount approximated by the voltage drop across the ESL. As the
load current increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value. Neglecting the
contribution of inductor current and regulator response, the output
voltage initially deviates by an amount shown in Equation 11.
ΔVMAX ≈
E
S
L
×
-d----i
dt
+ [ESR × ΔISTEP]
(EQ. 11)
The filter capacitors selected must have sufficiently low ESL and
ESR such that the total output voltage deviation is less than the
maximum allowable ripple.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but larger ESR.
Minimizing the ESL of the high-frequency capacitors allows them
to support the output voltage as the current increases.
Minimizing the ESR of the bulk capacitors allows them to supply
the increased current with less output voltage deviation.
Ceramic capacitors with X7R dielectric are recommended.
Alternately, a combination of low ESR solid tantalum capacitors
and ceramic capacitors with X7R dielectric may be used.
The ESR of the bulk capacitors is responsible for most of the
output voltage ripple. As the bulk capacitors sink and source the
inductor AC ripple current, a voltage, VP-P(MAX), develops across
the bulk capacitor according to Equation 12.
VP-P(MAX) = ESR × (---V-L--I--ON---U--–--T---V-×--O---f-U-s--T--×-)---V-V--O-I--N-U----T-
(EQ. 12)
16
FN8365.0
May 22, 2013
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