ISL6566ACRZ View Datasheet(PDF) - Intersil

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ISL6566ACRZ

Three-Phase Buck PWM Controller with Two Integrated MOSFET Drivers and One External Driver Signal

Intersil 

ISL6566A

Increased ripple frequency and lower ripple amplitude mean

that the designer can use less per-channel inductance and

lower total output capacitance for any performance

specification.

Figure 1 illustrates the multiplicative effect on output ripple

frequency. The three channel currents (IL1, IL2, and IL3)

combine to form the AC ripple current and the DC load

current. The ripple component has three times the ripple

frequency of each individual channel current. Each PWM

pulse is terminated 1/3 of a cycle after the PWM pulse of the

previous phase. The peak-to-peak current for each phase is

about 7A, and the dc components of the inductor currents

combine to feed the load.

To understand the reduction of ripple current amplitude in the

multi-phase circuit, examine the equation representing an

individual channel peak-to-peak inductor current.

IPP =

(---V----I--N-----–-----V----O-----U----T---)----V----O----U-----T-

L

fS

V

IN

(EQ. 1)

In Equation 1, VIN and VOUT are the input and output

voltages respectively, L is the single-channel inductor value,

and fS is the switching frequency.

The output capacitors conduct the ripple component of the

inductor current. In the case of multi-phase converters, the

capacitor current is the sum of the ripple currents from each

of the individual channels. Compare Equation 1 to the

expression for the peak-to-peak current after the summation

of N symmetrically phase-shifted inductor currents in

Equation 2. Peak-to-peak ripple current decreases by an

amount proportional to the number of channels. Output-

voltage ripple is a function of capacitance, capacitor

equivalent series resistance (ESR), and inductor ripple

current. Reducing the inductor ripple current allows the

designer to use fewer or less costly output capacitors.

IC, PP=

(---V----I--N-----–-----N------V----O-----U----T---)----V----O----U-----T-

L fS VIN

(EQ. 2)

Another benefit of interleaving is to reduce input ripple

current. Input capacitance is determined in part by the

maximum input ripple current. Multi-phase topologies can

improve overall system cost and size by lowering input ripple

current and allowing the designer to reduce the cost of input

capacitance. The example in Figure 2 illustrates input

currents from a three-phase converter combining to reduce

the total input ripple current.

The converter depicted in Figure 2 delivers 1.5V to a 36A load

from a 12V input. The RMS input capacitor current is 5.9A.

Compare this to a single-phase converter also stepping down

12V to 1.5V at 36A. The single-phase converter has 11.9A

RMS input capacitor current. The single-phase converter

must use an input capacitor bank with twice the RMS current

capacity as the equivalent three-phase converter.

INPUT-CAPACITOR CURRENT, 10A/DIV

CHANNEL 3

INPUT CURRENT

10A/DIV

CHANNEL 2

INPUT CURRENT

10A/DIV

CHANNEL 1

INPUT CURRENT

10A/DIV

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE

CONVERTER

Figures 22 and 23 in the section entitled Input Capacitor

Selection can be used to determine the input-capacitor RMS

current based on load current, duty cycle, and the number of

channels. They are provided as aids in determining the

optimal input capacitor solution.

PWM Operation

The timing of each converter leg is set by the number of

active channels. The default channel setting for the

ISL6566A is three. One switching cycle is defined as the

time between the internal PWM1 pulse termination signals.

The pulse termination signal is the internally generated clock

signal that triggers the falling edge of PWM1. The cycle time

of the pulse termination signal is the inverse of the switching

frequency set by the resistor between the FS pin and

ground. Each cycle begins when the clock signal commands

PWM1 to go low. The PWM1 transition signals the internal

channel-1 MOSFET driver to turn off the channel-1 upper

MOSFET and turn on the channel-1 synchronous MOSFET.

In the default channel configuration, the PWM2 pulse

terminates 1/3 of a cycle after the PWM1 pulse. The PWM3

pulse terminates 1/3 of a cycle after PWM2.

If EN_PH3 is connected to a +5V source, two channel

operation is selected and the PWM2 pulse terminates 1/2 of

a cycle after the PWM1 pulse terminates. If the BOOT2 and

PHASE2 pins are both connected to +12V, single channel

operation is selected.

Once a PWM pulse transitions low, it is held low for a

minimum of 1/3 cycle. This forced off time is required to

ensure an accurate current sample. Current sensing is

described in the next section. After the forced off time

expires, the PWM output is enabled. The PWM output state

is driven by the position of the error amplifier output signal,

VCOMP, minus the current correction signal relative to the

sawtooth ramp as illustrated in Figure 3. When the modified

9

FN9200.2

July 27, 2005

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