ISL6565ACR View Datasheet(PDF) - Intersil
Part Name
Description
View to exact match
ISL6565ACR Datasheet PDF : 28 Pages
| |||
ISL6565A, ISL6565B
Functional Pin Description
VCC - Supplies all the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply or through a series
300Ω resistor to a +12V supply.
GND - Bias and reference ground for the IC.
EN - This pin is a threshold-sensitive enable input for the
controller. Connecting the 12V supply to EN through an
appropriate resistor divider provides a means to synchronize
power-up of the controller and the MOSFET driver ICs.
When EN is driven above 1.31V, the ISL6565A, ISL6565B is
active depending on status of ENLL, the internal POR, and
pending fault states. Driving EN below 1.14V will clear all
fault states and prime the ISL6565A, ISL6565B to soft-start
when re-enabled.
ENLL - This pin is a logic-level enable input for the
controller. When asserted to a logic high, the ISL6565 is
active depending on status of EN, the internal POR, VID
inputs and pending fault states. Deasserting ENLL will clear
all fault states and prime the ISL6565A, ISL6565B to soft-
start when re-enabled.
FS - A resistor, placed from FS to ground, will set the
switching frequency. Refer to Equation 45 for proper resistor
calculation.
VID4, VID3, VID2, VID1, VID0, and VID12.5 - These are the
inputs to the internal DAC that provides the reference
voltage for output regulation. Connect these pins either to
open-drain outputs with or without external pull-up resistors
or to active-pull-up outputs. VID4-VID12.5 have 20µA
internal pull-up current sources that diminish to zero as the
voltage rises above the logic-high level.
VDIFF, VSEN, and RGND - VSEN and RGND are inputs to
the precision differential remote-sense amplifier. This
amplifier converts the differential voltage of the remote
output to a single-ended voltage referenced to local ground.
VDIFF is the amplifier’s output and the input to the regulation
and protection circuitry. Connect VSEN and RGND to the
sense pins of the remote load.
FB and COMP - Inverting input and output of the error
amplifier respectively. FB is connected to VDIFF through a
resistor. A negative current, proportional to output current is
present on the FB pin. A properly sized resistor between
VDIFF and FB sets the load line (droop). The droop scale
factor is set by the ratio of the ISEN resistors and the lower
MOSFET rDS(ON) or inductor DCR. COMP is tied back to FB
through an external R-C network to compensate the
regulator.
REF - The REF input pin is the positive input of the Error
Amp. It is internally connected to the DAC output through a
1kΩ resistor. A capacitor is used between the REF pin and
ground to smooth the voltage transition during Dynamic
VID™ operations.
TCOMP - Temperature compensation scaling input. A
resistor from this pin to ground sets the gain of the internal
thermal sense circuitry. The temperature sensed by the
controller is utilized to modify the droop current output to the
FB pin, adjusting for MOSFET rDS(ON) and Inductor DCR
variations with temperature.
PWM1, PWM2, PWM3 - Pulse-width modulation outputs.
Connect these pins to the PWM input pins of the Intersil
driver ICs. The number of active channels is determined by
the state of PWM3. Tie PWM3 to VCC to configure for
2-phase operation.
ISEN1, ISEN2, ISEN3, ICOMMON (ISL6565B only) -
These pins are used for sensing individual phase output
currents. The sensed current is used for channel balancing,
protection, and load line regulation. ISEN3 should be left
open for 2-phase operation.
For rDS(ON) current sensing using the ISL6565A, connect a
resistor between the ISEN1, ISEN2, and ISEN3 pins and
their respective phase node. This resistor sets a current
proportional to the current in the lower MOSFET during it’s
conduction interval.
For DCR sensing using the ISL6565B, connect a resistor
from VCORE to the ICOMMON pin. Then connect ISEN1,
ISEN2, and ISEN3 to the node between the RC sense
elements surrounding the inductor of their respective phase.
PGOOD - PGOOD is used as an indication of the end of
soft-start. It is an open-drain logic output that is low
impedance until the soft-start is completed. It will be pulled
low again once the undervoltage point is reached.
OFS - The OFS pin provides a means to program a dc
current for generating an offset voltage across the droop
resistor between FB and VDIFF. The offset current is
generated via an external resistor and precision internal
voltage references. The polarity of the offset is selected by
connecting the resistor to GND or VCC. For no offset, the
OFS pin should be left unconnected.
OVP - Overvoltage protection pin. This is an open drain
device, which can be externally configured with a resistor to
control an SCR to shut down the regulator.
9
|
|
Share Link: 