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ISL6236 View Datasheet(PDF) - Intersil

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ISL6236 Datasheet PDF : 35 Pages
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ISL6236
Pin Descriptions (Continued)
PIN
NUMBER
NAME
FUNCTION
21
GND Analog Ground for both SMPS and LDO. Connect externally to the underside of the exposed pad.
22
PGND Power Ground for SMPS controller. Connect PGND externally to the underside of the exposed pad.
23
LGATE2 SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC.
24
BOOT2 Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the typical application
circuits (Figures 66, 67 and 68). See “MOSFET Gate Drivers (UGATE, LGATE)” on page 27.
25
PHASE2 Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver.
PHASE2 is the current-sense input for the SMPS2.
26
UGATE2 High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE1 swings between PHASE2 and BOOT2.
27
EN2 SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than
the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start). Drive
EN2 below 0.8V to clear fault level and reset the fault latches.
28
POK2 SMP2 Power-Good Open-Drain Output. POK2 is low when the SMPS2 output voltage is more than 10% below the
normal regulation point or during soft-start. POK2 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK2 is low in shutdown.
29
SKIP Low-Noise Mode Control. Connect SKIP to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM
mode (fixed frequency). Connect to REF or leave floating for ultrasonic skip mode operation.
30
OUT2 SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. OUT2 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode.
31
ILIM2 SMPS2 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM2 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM2. Connect ILIM2 to REF for a fixed 200mV.
The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V.
32
REFIN2 Output voltage control for SMPS2. Connect REFIN2 to VCC for fixed 3.3V. Connect REFIN2 to VREF3 for fixed 1.05V.
REFIN2 can be used to program SMPS2 output voltage from 0.5V to 2.50V. SMPS2 output voltage is 0V if
REFIN2 <0.5V.
Typical Performance Curves
Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C.
7VIN SKIP MODE
7VIN PWM MODE
7VIN ULTRA SKIP MODE
12VIN SKIP MODE
12VIN PWM MODE
100
12VIN ULTRA SKIP MODE
25VIN SKIP MODE
25VIN PWM MODE
25VIN ULTRA SKIP MODE
90
80
70
60
50
40
30
20
10
0
0.001
0.010
0.100
1.000
OUTPUT LOAD (A)
10.000
FIGURE 1. VOUT2 = 1.05V EFFICIENCY vs LOAD (300kHz)
7VIN SKIP MODE
7VIN PWM MODE
7VIN ULTRA SKIP MODE
12VIN SKIP MODE
12VIN PWM MODE
100
12VIN ULTRA SKIP MODE
25VIN SKIP MODE
25VIN PWM MODE
25VIN ULTRA SKIP MODE
90
80
70
60
50
40
30
20
10
0
0.001
0.010
0.100
OUTPUT LOAD (A)
1.000
10.000
FIGURE 2. VOUT1 = 1.5V EFFICIENCY vs LOAD (200kHz)
8
FN6373.6
April 29, 2010
 

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