ISL6218CV View Datasheet(PDF) - Intersil

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ISL6218CV

Precision Single-Phase Buck PWM Controller for Intel Mobile Voltage Positioning IMVP-IV™ and IMVP-IV+™

Intersil 

ISL6218

VID

<3ms

CAPTURE VID CODE

VR_ON/EN

VCC-CORE

-12%

>10µs

t2

VBOOT

VVID

t1

PGOOD VCCP/VCC-MCH

3ms TO 12ms

PGOOD VCC-CORE

FIGURE 2. TIMING DIAGRAM SHOWING VR_ON, VCC_CORE AND PGOOD FOR VCC_CORE, VCCP AND VCC_MCH

Theory of Operation

Initialization

Once the +5VDC supply voltage (as connected to the

ISL6218 VDD pin) reaches the Power-On Reset (POR)

rising threshold, the PWM drive signals are held in

“Three-State” or high impedance mode. This results in both

the high side and low side MOSFETs being held off. Once

the supply voltage exceeds the POR rising threshold, the

controller will respond to a logic level high on the EN pin and

initiate the soft-start interval. If the supply voltage drops

below the POR falling threshold, POR shutdown is triggered

and the PWM outputs are again driven to “Three-State”.

The system signal, VR_ON is directly connected to the EN

pin of the ISL6218. Once the voltage on the EN pin rises

above 2.0V, the chip is enabled and soft-start begins. The

EN pin of the ISL6218 is also used to reset the ISL6218 for

cases when an undervoltage or overcurrent fault condition

has latched the IC off. Toggling the state of this pin to a level

below 1.0V will re-enable the IC. For the case of an

overvoltage fault, the VDD pin must be reset.

During start-up, the ISL6218 regulates to the voltage on the

STV pin. This is referred to as the “Boot” voltage and is

labeled VBOOT in Figure 2. Once power good signals are

received from the Vccp and Vcc_mch regulators, the

ISL6218 will capture the VID code and regulate, within 3ms

to 12ms, to this command voltage. The PGOOD pin of the

ISL6218 is both an input and an output and is further

described in “Fault Protection” on page 13.

Soft-Start Interval

Refer to Figure 2 and Figure 4. Once VDD rises above the

POR rising threshold and the EN pin voltage is above the

threshold of 2.0V, a soft-start interval is initiated. The voltage

on the EA+ pin is the reference voltage for the regulator. The

voltage on the EA+ pin is equal to the voltage on the SOFT

pin minus the “Droop” resistor voltage, VDROOP. During

start-up, when the voltage on SOFT is less than the “Boot”

voltage VBOOT, a 130µA current source I1, is used to slowly

ramp up the voltage on the soft-start capacitor CSOFT. This

slowly ramps up the reference voltage for the controller, and

controls the slew rate of the output voltage. The STV pin is

externally programmable and sets the start-up or “Boot”

voltage VBOOT. The programming of this voltage level is

explained in “STV, DSV and DRSV” on page 12.

The ISL6218 PGOOD pin is both an input and an output.

The system signal IMVP4_PWRGD is connected to power

good signals from the Vccp and Vcc_mch supplies. The

Intersil ISL6225 Dual Voltage Regulator is an ideal choice for

the Vccp and Vcc_mch supplies.

Refer to Figure 2 and Figure 4. Once the output voltage is

within the “Boot” level regulation limits and a logic high

PGOOD signal from the Vccp and Vccp_mch regulators is

received, the ISL6218 is enabled to capture the VID code

and regulate to that command voltage.

The “Droop” current source IDROOP, is proportional to load

current. This current source is used to reduce the reference

voltage on EA+ by the voltage drop across the “Droop”

resistor. A more in-depth explanation of “Droop” and the

sizing of this resistor can be found in “Droop Compensation”

on page 14.

8

FN9101.6

August 6, 2007

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