ISL6217ACVZ View Datasheet(PDF) - Intersil

Part Name

Description

View to exact match

ISL6217ACVZ

Precision Multi-Phase Buck PWM Controller for Intel, Mobile Voltage Positioning IMVP-IV™ and IMVP-IV+™

Intersil 

ISL6217A

Active, Deep Sleep and Deeper Sleep Modes

The ISL6217A Multi-Phase Controller is designed to control

the CORE output voltage as per the IMVP-IV™ and

IMVP-IV+™ specifications for Active, Deep Sleep, and

Deeper Sleep Modes of Operation.

After initial Start-up, a logic high signal on DSEN# and a

logic low signal on DRSEN signals the ISL6217A to operate

in Active mode. Refer to Table 2. This mode will recognize

VID code changes and regulate the output voltage to these

command voltages.

TABLE 2. OUTPUT VOLTAGE AS A FUNCTION OF DSEN#

AND DRSEN LOGIC STATES

DSEN# -

STP_CPU#

DRSEN -

DPRSLPVR

MODE OF OUTPUT

OPERATION VOLTAGE

1

0

Active

VID

0

0

Deep Sleep

DSV

0

1

Deeper Sleep DRSV

1

1

Deeper Sleep DRSV

VID[0..5]

VCC_CORE

Current VID Code

<600ns

Current Voltage Level

New VID Code

New Voltage Level

PGOOD HIGH

FIGURE 5. PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING

VID[0..5]

STP_CPU#

(DSEN#)

VCC_CORE

VID Code remains the same

VID Command Voltage

VDeep Sleep

<30us

FIGURE 6. VCORE RESPONSE FOR DEEPER SLEEP COMMAND

VID[0..5]

VID Code remains the same

STP_CPU#

(DSEN#)

DPRSLPVR

(DRSEN)

VCC_CORE

VDeep Sleep

VDeeper Sleep

Deeper Sleep Mode

Short DPRSLP causes

VCC-CORE to ramp up

FIGURE 7. VCORE RESPONSE FOR DEEPER SLEEP COMMAND

11

FN9107.3

June 30, 2005

Share Link: