ISL6217CVZA View Datasheet(PDF) - Intersil
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ISL6217CVZA Datasheet PDF : 19 Pages
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ISL6217
ISL6217
250
I1
I2
IDROOP
Error
Amplifier
+
SOFT
R DROOP
EA+
+ V DROOP
C SOFT
FIGURE 3.
SOFT-START TRACKING CIRCUITRY SHOWING
INTERNAL CURRENT SOURCES AND "DROOP"
FOR ACTIVE, DEEP AND DEEPER SLEEP
MODES OF OPERATION
The “Droop” current source, IDROOP, is proportional to
load current. This current source is used to reduce the
reference voltage on EA+ by the voltage drop across the
“Droop” resistor. A more in-depth explanation of “Droop”,
and the sizing of this resistor, can be found in the “Droop
Compensation” section of this document.
The choice of value for soft start capacitor is determined by
the maximum slew rate required for the application. An
example calculation is shown below. Using the combined I1
and I2 current sources on the SOFT pin as 130mA, and the
worst case slew rate of (10mV/µs), the SOFT capacitor is
calculated as follows:
CSOFT
=
ISOURCE
SlewRate
= 130µA × 1µs
10mV
= 0.013µF
≈ 0.012µF
(EQ. 1)
Gate-Drive Signals
The ISL6217 provides internal gate-drive for a two channel,
Synchronous Buck, Core Regulator. During two channel
mode of operation, the PWM drive signals are switched
180° out of phase to reduce ripple current delivered from
the DC rail and to the load.
The ISL6217 was designed with a 4 amp, low-side gate
current sinkability, and a 2 amp low-side gate current
source ability, to efficiently drive the latest, high-
performance MOSFETs. This feature will provide the
system designer with flexibility in MOSFET selection, as
well as optimum efficiency during Active mode of operation.
200
150
100
50
0
250
500
750
1000
Channel Switching Frequency, Fsw,
()
FIGURE 4. CHANNEL SWITCHING FREQUENCY VS. RFSET
PWRCH pin
A HIGH logic level on this pin enables two channel
operation and a LOW logic signal enables single channel
operation. By tying this pin to the STP_CPU# system
signal, (DSEN# pin on ISL6217) single channel operation
will be invoked during the light loading of both Deep and
Deeper Sleep. If single channel operation is desired only
during Deeper Sleep, the inversion of system signal
DPRSLPVR can be connected to this pin.
The aggressive gate-drive capability of ISL6217, coupled
with the single channel operation feature results in superior
efficiency performance over both light and heavy loads.
Frequency Setting
Both channel switching frequencies are set up by a resistor
from the FSET pin to ground. The choice of FSET
resistance for a desired switching frequency can be
approximated using Figure 4. The switching frequency is
designed to operate between 250kHz and 1MHz per
phase.
CORE Voltage Programming
The voltage identification pins (VID0, VID1, VID2, VID3,
VID4 and VID5) set the DAC output voltage. These pins do
not have internal pull-up or pull-down capability. These pins
will recognize 1.0V, 3.3V, or 5.0V CMOS logic. Table 1
shows the command voltage, VDAC for the 6 bit VID
codes.
The IC responds to VID code changes as shown in
Figure 5. PGOOD is masked between these transitions.
9
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