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ISL6208CRZ View Datasheet(PDF) - Intersil

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ISL6208CRZ Datasheet PDF : 13 Pages
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Timing Diagram
ISL6208, ISL6208B
PWM
tPDHU
tPDLU
tRU
2.5V
tFU
1V
UGATE
LGATE
1V
tFL
tRL
tPDLL
tPDHL
Functional Pin Description
UGATE
The UGATE pin is the upper gate drive output. Connect to the
gate of high-side power N-Channel MOSFET.
BOOT
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See “Internal Bootstrap Diode” on
page 8 for guidance in choosing the appropriate capacitor
value.
PWM
The PWM signal is the control input for the driver. The PWM signal
can enter three distinct states during operation. See “Three-State
PWM Input” on page 8 for further details. Connect this pin to the
PWM output of the controller.
GND
GND is the ground pin for the IC.
LGATE
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC
Connect the VCC pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
FCCM
The FCCM pin enables or disables Diode Emulation. When
FCCM is LOW, diode emulation is allowed. Otherwise,
continuous conduction mode is forced. See “Diode Emulation”
on page 8 for more detail.
tTSSHD
tRU
tFU
tPTS
tPTS
tTSSHD
tFL
PHASE
Connect the PHASE pin to the source of the upper MOSFET and
the drain of the lower MOSFET. This pin provides a return path
for the upper gate driver.
Description
Theory of Operation
Designed for speed, the ISL6208 dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one
externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower MOSFET
(see “Timing Diagram” above). After a short propagation delay
[tPDLL], the lower gate begins to fall. Typical fall times [tFL] are
provided in the “Electrical Specifications” section. Adaptive shoot-
through circuitry monitors the LGATE voltage. When LGATE has
fallen below 1V, UGATE is allowed to turn ON. This prevents both
the lower and upper MOSFETs from conducting simultaneously, or
shoot-through.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLU] is encountered before the upper gate
begins to fall [tFU]. The upper MOSFET gate-to-source voltage is
monitored, and the lower gate is allowed to rise after the upper
MOSFET gate-to-source voltage drops below 1V. The lower gate
then rises [tRL], turning on the lower MOSFET.
This driver is optimized for converters with large step-down
compared to the upper MOSFET because the lower MOSFET
conducts for a much longer time in a switching period. The
lower gate driver is therefore sized much larger to meet this
application requirement.
The 0.5Ω ON-resistance and 4A sink current capability enable
the lower gate driver to absorb the current injected to the lower
gate through the drain-to-gate capacitor of the lower MOSFET
and prevent a shoot-through caused by the high dv/dt of the
phase node.
6
FN9115.5
November 22, 2011
 

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