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ISL6207CB View Datasheet(PDF) - Intersil

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ISL6207CB Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
ISL6207
The next larger standard value capacitance is 0.22µF. A
good quality ceramic capacitor is recommended.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
QGATE = 100nC
0.4
50nC
0.2
20nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VBOOT(V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
P
=
fs
w
( 1.5
VU
Q
U
+
VL
Q
L
)
+
IDDQ
V
C
C
where fsw is the switching frequency of the PWM signal. VU
and VL represent the upper and lower gate rail voltage. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The IDDQ VCC product is the quiescent power
of the driver and is typically negligible.
1000
900
800
700
QU=100nC
QL=200nC
QU=50nC
QL=100nC
QU=50nC
QL=50nC
600
QU=20nC
500
QL=50nC
400
300
200
100
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 3. POWER DISSIPATION vs FREQUENCY
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and the power devices
(both upper and lower FETs) could cause serious ringing,
exceeding absolute maximum rating of the devices. The
negative ringing at the edges of the PHASE node could add
charges to the bootstrap capacitor through the internal
bootstrap diode, in some cases, it could cause over stress
across BOOT and PHASE pins. Therefore, user should do a
careful layout and select proper MOSFETs and drivers. The
D2PAK and DPAK package MOSFETs have high parasitic
lead inductance, which can exacerbate this issue. FET
selection plays an important role in reducing PHASE ring. If
higher inductance FETs must be used, a Schottky diode is
recommended across the lower MOSFET to clamp negative
PHASE ring.
A good layout would help reduce the ringing on the phase
and gate nodes significantly:
• Avoid uses via for decoupling components across BOOT
and PHASE pins and in between VCC and GND pins. The
decoupling loop should be short.
• All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using via; otherwise,
use two vias for interconnection when possible.
• Keep SOURCE of upper FET and DRAIN of lower FET as
close as thermally possible.
• Keep connection in between SOURCE of lower FET and
power ground wide and short.
• Input capacitors should be placed as close to the DRAIN
of upper FET and SOURCE of lower FETs as thermally
possible.
Note: Refer to Intersil Tech Brief TB447 for more information.
6
FN9075.7
July 25, 2005
 

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