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ISL6152IB View Datasheet(PDF) - Intersil

Part Name
Description
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ISL6152IB Datasheet PDF : 23 Pages
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ISL6142, ISL6152
Test Circuit and Timing Diagrams (Continued)
VEE - VDRAIN = 0V
VDH
DRAIN
VDRAIN - VEE = 8.0V
8.0V
tPLHDH
PWRGD
1.0V
VDH
DRAIN
VEE - VDRAIN = 0V
PWRGD
VDRAIN - VEE = 8.0V
8.0V
tPHLDH
1.0V
VPWRGD - VDRAIN = 0V
FIGURE 6A. DRAIN HIGH TO PWRGD (INACTIVE) HIGH
(ISL6142)
FIGURE 6B. DRAIN HIGH TO PWRGD (INACTIVE) LOW
(ISL6152)
FIGURE 6. DRAIN TO PWRGD/PWRGD INACTIVE TIMING
3V
DIS
0V
GATE
13.6V
0V
1.50V
tPHLDIS tPLHDIS
1V
2.2V
1V
FIGURE 7. DISABLE TO GATE TIMING (ISL6142/52)
GATE
VGATE - VGATE = 0V
FAULT
tPHLF
1.4V
1.0V
FIGURE 8. FAULT TO GATE TIMING (ISL6142/52)
50mV
0V
13.6V
SENSE
GATE
tPHLSENSE
~4V (depends on FET threshold)
SENSE
0V
13.6V
GATE
210mV
tPHLHF
VEE
FIGURE 9. SENSE TO GATE (CURRENT LIMIT) TIMING
FIGURE 10. SENSE TO GATE (HARD FAULT) TIMING
UV
tPHLCB
GATE
1.0V
1.0V
Over-Current Time-Out
FIGURE 11. CURRENT LIMIT TO GATE TIMING
VSENSE
VOUT
tR
90%
10%
90%
tF
10%
FIGURE 12. OUTPUT CURRENT RISE AND FALL TIME
10
 

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