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ISL6151IB(2002) View Datasheet(PDF) - Intersil

Part Name
Description
View to exact match
ISL6151IB
(Rev.:2002)
Intersil
Intersil Intersil
ISL6151IB Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
GND
R4
UV
R5
OV
R6
-
1.265V +
+-
VEE VEE
-
1.255V +
+-
VEE +
1.255V -
+-
VEE
-
210mV +
+-
VEE
-
50mV +
+-
VEE
ISL6141, ISL6151
VDD
UVLO
UV
REGULATOR,
REFERENCES
13V
OV
LOGIC
TIMING
GATE DRIVE
HARD
FAULT
GATE
CURRENT
LIMIT
REGULATOR
600ยตs
TIMER
GATE
-
11.1V +
+-
VEE -
1.3V +
+-
VEE
OUTPUT
DRIVE
LATCH
LOGIC
PWRGD
PWRGD
PWRGD
(ISL6141)
PWRGD
(ISL6151)
GND
VEE
SENSE
GATE
DRAIN
R3 C2
R2
C1
LOAD
CL
RL
-48V IN
R1
Q1
FIGURE 1. BLOCK DIAGRAM
-48V OUT
Pin Descriptions
PWRGD (ISL6141; L Version) Pin 1
This digital output is an open-drain pull-down device. During
start-up the DRAIN and GATE voltages are monitored with
two separate comparators. The first comparator looks at the
DRAIN pin voltage compared to the internal VPG reference
(VPG is nominal 1.3V); this measures the voltage drop across
the external FET and sense resistor. When the DRAIN to VEE
voltage drop is less than 1.3V, the first of two conditions
required for the power to be considered good are met. In
addition, the GATE voltage monitored by the second
comparator must be within approximately 2.5V of its normal
operating voltage (13.6V). When both criteria are met the
PWRGD output will transition from high to low, enabling a
power module in some applications. The output is latched in
the low state until any of the signals that shut off the GATE
occur (Over-Voltage, Under-Voltage, Under-Voltage Lock-
Out, Over-Current Time-Out, or powering down). Any of these
conditions will re-set the latch and the PWRGD output will
transition from low to high indicating power is no longer good.
In this case the output pull-down device shuts off, and the pin
becomes high impedance. Typically an external pull-up of
some kind is used to pull the pin high (many brick regulators
have a pull-up function built in).
PWRGD (ISL6151; H Version) Pin 1 - This digital
output is used to provide an active high signal to enable an
external module. The Power Good comparators are the
2
 

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