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ISL29010IROZ-T7 View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL29010IROZ-T7 Light-to-Digital Output Sensor with High Sensitivity, Gain Selection, and I2C Interface Intersil
Intersil Intersil
ISL29010IROZ-T7 Datasheet PDF : 14 Pages
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ISL29010
Pin Descriptions
PIN NUMBER
1
2
3
PIN NAME
VDD
GND
REXT
4
A0
5
SCL
6
SDA
DESCRIPTION
Positive supply; connect this pin to a regulated 2.5V to 3.3V supply
Ground pin. The thermal pad is connected to the GND pin
External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100kΩ resistor with
1% tolerance
Bit 0 of I2C address
I2C serial clock
The I2C bus lines can pulled above VDD, 5.5V max.
I2C serial data
Principles of Operation
Photodiodes
The ISL29010 contains two photodiode arrays which convert
light into current. Some diodes are sensitive to both visible
and infrared light, while the others are only sensitive to
infrared light. Using the infrared portion of the light as
baseline, the visible light can be extracted. The spectral
response vs wavelength is shown in Figure 7 in the “Typical
Performance Curves” on page 10. After light is converted to
current during the light data process, the current output is
converted to digital by a single built-in integrating type signed
15-bit Analog-to-Digital Converter (ADC). An I2C command
reads the visible light intensity in counts.
The converter is a charge-balancing integrating type signed
15-bit ADC. The chosen method for conversion is best for
converting small current signals in the presence of an AC
periodic noise. A 100ms integration time, for instance, highly
rejects 50Hz and 60Hz power line noise simultaneously. See
“Integration Time or Conversion Time” on page 7 and “Noise
Rejection” on page 8.
The built-in ADC offers user flexibility in integration time or
conversion time. There are two timing modes: Internal Timing
Mode and External Timing Mode. In Internal Timing Mode,
integration time is determined by an internal dual speed
oscillator (fOSC), and the n-bit (n = 4, 8, 12, 16) counter inside
the ADC. In External Timing Mode, integration time is
determined by the time between two consecutive I2C External
Timing Mode commands. See External Timing Mode example.
A good balancing act of integration time and resolution
(depending on the application) is required for optimal results.
The ADC has four I2C programmable range select to
dynamically accommodate various lighting conditions. For
very dim conditions, the ADC can be configured at its lowest
range. For very bright conditions, the ADC can be configured
at its highest range.
I2C Interface
There are eight (8) 8-bit registers available inside the ISL29010.
The command and control registers define the operation of the
device. The command and control registers do not change until
the registers are overwritten. There are two 8-bit registers that
set the high and low interrupt thresholds. There are four 8-bit
data Read Only registers, two bytes for the sensor reading and
another two bytes for the timer counts. The data registers
contain the ADC's latest digital output, and the number of clock
cycles in the previous integration period.
The ISL29010 has a 7-bit I2C interface slave address. The
six most significant bits are hardwired internally as 100010
while the least significant bit A0 can be either connected to
Ground or VDD to allow two possible addresses 1000100 or
1000101. When 1000100x or 1000101x with x as R or W is
sent after the Start condition, this device compares the first
seven bits of this byte to its address and matches.
Figure 1 shows a sample one-byte read. Figure 2 shows a
sample one-byte write. Figure 3 shows a sync_I2C timing
diagram sample for externally controlled integration time.
The I2C bus master always drives the SCL (clock) line, while
either the master or the slave can drive the SDA (data) line.
Figure 2 shows a sample write. Every I2C transaction begins
with the master asserting a start condition (SDA falling while
SCL remains high). The following byte is driven by the
master, and includes the slave address and read/write bit.
The receiving device is responsible for pulling SDA low
during the acknowledgement period.
Every I2C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high).
For more information about the I2C standard, please consult
the Philips® I2C specification documents.
3
FN6414.0
February 13, 2008
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