COUNTER is the number increments accrued for between
integration time for External Timing Mode.
Gain/Range, Range (k)
The Gain/Range can be programmed in the control register
to give Range (k) determining the FSR. Note that Range(k)
is not the FSR (see Equation 3). Range(k) provides four
constants depending on programmed k that will be scaled by
REXT (see Table 9). Unlike REXT, Range(k) dynamically
adjusts the FSR. This function is especially useful when light
conditions are varying drastically while maintaining excellent
Number of Clock Cycles, n-bit ADC
The number of clock cycles determines “n” in the n-bit ADC; 2n
clock cycles is a n-bit ADC. n is programmable in the command
register in the width function. Depending on the application, a
good balance of speed and resolution has to be considered
when deciding for n. For fast and quick measurement, choose
the smallest n = 4. For maximum resolution without regard of
time, choose n = 16. Table 12 compares the trade-off between
integration time and resolution. See Equations 10 and 11 for the
relation between integration time and n. See Equation 3 for the
relation of n and resolution.
TABLE 12. RESOLUTION AND INTEGRATION TIME
fOSC = 327kHz
fOSC = 655kHz
tINT (ms) LUX/COUNT tINT (ms) (LUX/COUNT)
REXT = 100kΩ
External Scaling Resistor REXT and fosc
The ISL29003 uses an external resistor REXT to fix its
internal oscillator frequency, fOSC. Consequently, REXT
determines the fOSC, integration time and the FSR of the
device. fOSC, a dual speed mode oscillator, is inversely
proportional to REXT. For user simplicity, the proportionality
constant is referenced to fixed constants 100kΩ and
fOSC1 is oscillator frequency when Range1 or Range2 are
set. This is nominally 327kHz when REXT is 100kΩ.
fOSC2 is the oscillator frequency when Range3 or Range4
are set. This is nominally 655kHz when REXT is 100kΩ.
When the Range/Gain bits are set to Range1 or Range2,
fOSC runs at half speed compared to when Range/Gain bits
are set to Range3 and Range4.
The automatic fOSC adjustment feature allows significant
improvement of signal-to-noise ratio when detecting very low
Integration Time or Conversion Time
Integration time is the period during which the device’s
analog-to-digital ADC converter samples the photodiode
current signal for a lux measurement. Integration time, in
other words, is the time to complete the conversion of analog
photodiode current into a digital signal (number of counts).
Integration time affects the measurement resolution. For
better resolution, use a longer integration time. For short and
fast conversions use a shorter integration time.
The ISL29003 offers user flexibility in the integration time to
balance resolution, speed and noise rejection. Integration time
can be set internally or externally and can be programmed in
the command register 00(hex) bit 5.
INTEGRATION TIME IN INTERNAL TIMING MODE
This timing mode is programmed in the command register
00(hex) bit 5. Most applications will be using this timing
mode. When using the Internal Timing Mode, fOSC and
n-bits resolution determine the integration time. tint is a
function of the number of clock cycles and fOSC.
2n × ----1------
for Internal Timing Mode only
n = 4, 8, 12, and16. n is the number of bits of resolution.
Therefore, 2n is the number of clock cycles. n can be
programmed at the command register 00(hex) bits 1 and 0.
Since fOSC is dual speed depending on the Gain/Range bit,
tint is dual time. The integration time as a function of REXT
and n is:
327kHz × 100kΩ
tint1 is the integration time when the device is configured for
Internal Timing Mode and Gain/Range is set to Range1 or
655kHz × 100kΩ
tint2 is the integration time when the device is configured for
Internal Timing Mode and Gain/Range is set to Range3 or
August 8, 2008