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ISL22343WFV20Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL22343WFV20Z Quad Digitally Controlled Potentiometer (XDCP™) Intersil
Intersil Intersil
ISL22343WFV20Z Datasheet PDF : 19 Pages
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ISL22343
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 21) (Note 5) (Note 21)
SERIAL INTERFACE SPECS
VIL
A1, A0, A2, SDA, and SCL
Input Buffer LOW Voltage
0.3*VCC
VIH
A1, A0, A2, SDA, and SCL
Input Buffer HIGH Voltage
0.7*VCC
Hysteresis SDA and SCL Input Buffer
(Note 19) Hysteresis
0.05*VCC
VOL
SDA Output Buffer LOW
(Note 19) Voltage, Sinking 4mA
0
0.4
Cpin
A1, A0, A2, SDA, and SCL
10
(Note 19) Pin Capacitance
fSCL
SCL Frequency
400
tsp
Pulse Width Suppression Any pulse narrower than the max spec is suppressed
50
Time at SDA and SCL
Inputs
tAA
SCL Falling Edge to SDA SCL falling edge crossing 30% of VCC, until SDA exits
900
(Note 19) Output Data Valid
the 30% to 70% of VCC window
tBUF
(Note 19)
Time the Bus Must be Free SDA crossing 70% of VCC during a STOP condition, to
Before the Start of a New SDA crossing 70% of VCC during the following START
Transmission
condition
1300
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
Clock LOW Time
Clock HIGH Time
START Condition Setup
Time
START Condition Hold
Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup
Time
STOP Condition Hold
Time for Read, or Volatile
Only Write
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both crossing 70%
of VCC
From SDA falling edge crossing 30% of VCC to SCL
falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC window, to
SCL rising edge crossing 30% of VCC
From SCL rising edge crossing 70% of VCC to SDA
entering the 30% to 70% of VCC window
From SCL rising edge crossing 70% of VCC, to SDA
rising edge crossing 30% of VCC
From SDA rising edge to SCL falling edge; both
crossing 70% of VCC
1300
600
600
600
100
0
600
1300
tDH
Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA
0
(Note 19)
enters the 30% to 70% of VCC window
tR
SDA and SCL Rise Time From 30% to 70% of VCC
(Note 19)
20 +
250
0.1*Cb
tF
SDA and SCL Fall Time
(Note 19)
From 70% to 30% of VCC
20 +
250
0.1*Cb
UNIT
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
FN6423.2
August 17, 2015
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