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ISL22343UFV20Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL22343UFV20Z Quad Digitally Controlled Potentiometer (XDCP?) Intersil
Intersil Intersil
ISL22343UFV20Z Datasheet PDF : 19 Pages
First Prev 11 12 13 14 15 16 17 18 19
ISL22343
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 0
ADDRESS
BYTE
S
T
A IDENTIFICATION
R BYTE WITH
T
R/W = 1
A
A
C
C
K
K
S
AT
CO
KP
SIGNAL AT SDA 1 0 1 0 A2 A1 A0 0 0 0 0 0
A
SIGNALS FROM
C
THE SLAVE
K
1 0 1 0 A2 A1 A0 1
A
A
C
C FIRST READ
K
K DATA BYTE
FIGURE 19. READ SEQUENCE
LAST READ
DATA BYTE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22343 responds with an ACK. At this time, the device
enters its standby state (see Figure 18).
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write. Thus, non-volatile registers must be
written individually.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (see Figure 19). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL22343 responds with an ACK. Then the ISL22343
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The Data Bytes are from the registers indicated by an
internal pointer. This pointers initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 0Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.The master terminates the read
operation issuing a NACK (ACK) and a STOP condition
following the last bit of the last Data Byte (See Figure 19).
Applications Information
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients (or overshoot/undershoot) resulting from the
sudden transition from a very low impedance “make” to a
much higher impedance “break within an extremely short
period of time (<50ns). Two such code transitions are EFh to
F0h, and 0Fh to 10h. Note that all switching transients will
settle well within the settling time as stated on the datasheet.
A small capacitor can be added externally to reduce the
amplitude of these voltage transients, but that will also
reduce the useful bandwidth of the circuit, thus this may not
be a good solution for some applications. It may be a good
idea, in that case, to use fast amplifiers in a signal chain for
fast recovery.
Application Example
Figure 20 shows an example of using ISL22343 for gain
setting and offset correction in a high side current
measurement application. DCP0 applies a programmable
offset voltage of ±25mV to the FB+ pin of the Instrumentation
Amplifier ISL28272 to adjust output offset to zero voltages.
DCP1 programs the gain of the ISL28272 from 90 to 110
with 5V output for 10A current through current sense
resistor. DCP2 and DCP3 are used for another channel of
dual ISL28272 correspondently (not shown in Figure 20).
More application examples can be found at
http://www.intersil.com/data/an/AN1145.pdf
15
FN6423.2
August 17, 2015
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