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ISL22343UFV20Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL22343UFV20Z Quad Digitally Controlled Potentiometer (XDCP?) Intersil
Intersil Intersil
ISL22343UFV20Z Datasheet PDF : 19 Pages
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ISL22343
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK (Acknowledge) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
The ISL22343 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22343 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 1010 as four MSBs, and
the following three bits matching the logic values present at
pins A2, A1 and A0. The LSB is the Read/Write bit. Its value
is “1” for a Read operation and “0” for a Write operation (See
Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY
1
0
1
0
A2
A1
A0 R/W
(MSB)
(LSB)
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM
THE MASTER
WRITE
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
1 0 1 0 A2 A1 A0 0 0 0 0 0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
FIGURE 18. BYTE WRITE SEQUENCE
14
FN6423.2
August 17, 2015
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