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ISL22313 View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL22313 Single Digitally Controlled Potentiometer (XDCP™) Intersil
Intersil Intersil
ISL22313 Datasheet PDF : 15 Pages
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ISL22313
Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by
characterization. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 18) (Note 4) (Note 18)
SERIAL INTERFACE SPECS
VIL
A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*VCC
VIH
A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*VCC
VCC + 0.
3
Hysteresis SDA and SCL input buffer hysteresis
(Note 16)
0.05*VCC
VOL
SDA output buffer LOW voltage,
(Note 16) sinking 4mA
0
0.4
Cpin A1, A0, SDA, and SCL pin
10
(Note 16) capacitance
fSCL
SCL frequency
400
tsp
Pulse width suppression time at SDA Any pulse narrower than the max spec is
50
and SCL inputs
suppressed
tAA
SCL falling edge to SDA output data SCL falling edge crossing 30% of VCC, until
900
(Note 16) valid
SDA exits the 30% to 70% of VCC window
tBUF
(Note 16)
Time the bus must be free before the SDA crossing 70% of VCC during a STOP
start of a new transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
tLOW
tHIGH
tSU:STA
Clock LOW time
Clock HIGH time
START condition setup time
tHD:STA START condition hold time
tSU:DAT Input data setup time
tHD:DAT Input data hold time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
tSU:STO
tHD:STO
tDH
(Note 16)
STOP condition setup time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
STOP condition hold time for read, or From SDA rising edge to SCL falling edge;
volatile only write
both crossing 70% of VCC
Output data hold time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
600
1300
0
tR
SDA and SCL rise time
(Note 16)
From 30% to 70% of VCC
20 +
250
0.1 * Cb
tF
SDA and SCL fall time
(Note 16)
From 70% to 30% of VCC
20 +
250
0.1 * Cb
Cb
Capacitive loading of SDA or SCL
(Note 16)
Total on-chip and off-chip
10
400
Rpu
SDA and SCL bus pull-up resistor
Maximum is determined by tR and tF
1
(Note 16) off-chip
For Cb = 400pF, max is about 2kΩ~2.5kΩ
For Cb = 40pF, max is about 15kΩ~20kΩ
UNIT
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
6
FN6421.0
July 17, 2007
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