ISL22313TFU10Z-TK View Datasheet(PDF) - Intersil
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ISL22313TFU10Z-TK Datasheet PDF : 15 Pages
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ISL22313
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM
THE MASTER
WRITE
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
1 0 1 0 0 A1 A0 0 0 0 0 0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
FIGURE 18. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 0
ADDRESS
BYTE
S
T
A IDENTIFICATION
R BYTE WITH
T
R/W = 1
A
A
C
C
K
K
S
AT
CO
KP
SIGNAL AT SDA 1 0 1 0 0A1 A0 0 0 0 0 0
A
SIGNALS FROM
C
THE SLAVE
K
1 0 1 0 0 A1 A0 1
A
A
C
C FIRST READ
K
K DATA BYTE
LAST READ
DATA BYTE
FIGURE 19. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22313 responds with an ACK. At this time, the device
enters its standby state (see Figure 18).
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write. Thus, non-volatile registers must be
written individually.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (see Figure 19). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL22313 responds with an ACK. Then the ISL22313
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
13
FN6421.0
July 17, 2007
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