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ISL2101AAR3Z-T View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL2101AAR3Z-T 100V, 2A Peak, High Frequency Half-Bridge Drivers Intersil
Intersil Intersil
ISL2101AAR3Z-T Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
ISL2100A, ISL2101A
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = +25°C
MIN TYP MAX
TJ = -40°C to
+125°C
MIN MAX
UNITS
HB Threshold Hysteresis
BOOTSTRAP DIODE
VHBH
-
0.6
-
-
-
V
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
LO GATE DRIVER
VDL
VDH
RD
IVDD-HB = 100µA
IVDD-HB = 100mA
IVDD-HB = 100mA
-
0.5 0.6
-
0.7
V
-
0.7 0.9
-
1
V
-
0.8
1
-
1.5
Ω
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
Peak Pull-Down Current
HO GATE DRIVER
VOLL
VOHL
IOHL
IOLL
ILO = 100mA
ILO = -100mA,
VOHL = VDD - VLO
VLO = 0V
VLO = 12V
-
0.25 0.3
-
0.4
V
-
0.25 0.3
-
0.4
V
-
2
-
-
-
A
-
2
-
-
-
A
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
Peak Pull-Down Current
VOLH
VOHH
IOHH
IOLH
IHO = 100mA
IHO = -100mA,
VOHH = VHB - VHO
VHO = 0V
VHO = 12V
-
0.25 0.3
-
0.4
V
-
0.25 0.3
-
0.4
V
-
2
-
-
-
A
-
2
-
-
-
A
Electrical Specifications
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise
Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = +25°C
MIN TYP MAX
TJ = -40°C
to +125°C
MIN MAX UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
Delay Matching: Upper Turn-Off to Lower Turn-On
Delay Matching: Lower Turn-Off to Upper Turn-On
Either Output Rise/Fall Time (10% to 90%/90% to 10%)
Either Output Rise/Fall Time (3V to 9V/9V to 3V)
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
tLPHL
tHPHL
tLPLH
tHPLH
tMON
tMOFF
tRC,tFC
tR,tF
tPW
tBS
CL = 1nF
CL = 0.1µF
-
34 50
-
60
ns
-
31 50
-
60
ns
-
39 50
-
60
ns
-
39 50
-
60
ns
1
8
-
-
16
ns
1
6
-
-
16
ns
-
10
-
-
-
ns
- 0.5 0.6 - 0.8 us
-
-
-
-
50
ns
-
10
-
-
-
ns
5
FN6294.3
May 6, 2010
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