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ISL1209IU10Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL1209IU10Z Low Power RTC with Battery Backed SRAM and Event Detection Intersil
Intersil Intersil
ISL1209IU10Z Datasheet PDF : 24 Pages
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ISL1209
I2C Interface Specifications Test Conditions:VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 4) MAX UNITS
VIL
SDA and SCL input buffer LOW
voltage
VIH
SDA and SCL input buffer HIGH
voltage
Hysteresis SDA and SCL input buffer hysteresis
VOL
SDA output buffer LOW voltage,
VDD = 5V, IOL = 3mA
sinking 3mA
-0.3
0.7 x
VDD
0.05 x
VDD
0.3 x
V
VDD
VDD +
V
0.3
V
0.4
V
Cpin
fSCL
tIN
SDA and SCL pin capacitance
SCL frequency
TA = 25°C, f = 1MHz, VDD = 5V, VIN = 0V,
VOUT = 0V
Pulse width suppression time at SDA Any pulse narrower than the max spec is
and SCL inputs
suppressed.
10
pF
400
kHz
50
ns
tAA
tBUF
SCL falling edge to SDA output data
valid
Time the bus must be free before the
start of a new transmission
SCL falling edge crossing 30% of VDD, until SDA
exits the 30% to 70% of VDD window.
SDA crossing 70% of VDD during a STOP
condition, to SDA crossing 70% of VDD during
the following START condition.
1300
900
ns
ns
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
Clock LOW time
Clock HIGH time
START condition setup time
START condition hold time
Input data setup time
tHD:DAT
Input data hold time
tSU:STO STOP condition setup time
tHD:STO STOP condition hold time
tDH
Output data hold time
tR
SDA and SCL rise time
Measured at the 30% of VDD crossing.
1300
Measured at the 70% of VDD crossing.
600
SCL rising edge to SDA falling edge. Both
600
crossing 70% of VDD.
From SDA falling edge crossing 30% of VDD to 600
SCL falling edge crossing 70% of VDD.
From SDA exiting the 30% to 70% of VDD
100
window, to SCL rising edge crossing 30% of
VDD.
From SCL falling edge crossing 30% of VDD to
0
SDA entering the 30% to 70% of VDD window.
From SCL rising edge crossing 70% of VDD, to 600
SDA rising edge crossing 30% of VDD.
From SDA rising edge to SCL falling edge. Both 600
crossing 70% of VDD.
From SCL falling edge crossing 30% of VDD,
0
until SDA enters the 30% to 70% of VDD window.
From 30% to 70% of VDD.
20 +
0.1 x Cb
ns
ns
ns
ns
ns
900
ns
ns
ns
ns
300
ns
tF
SDA and SCL fall time
From 70% to 30% of VDD.
20 +
0.1 x Cb
300
ns
Cb
Capacitive loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF.
1
k
chip
For Cb = 400pF, max is about 2~2.5k.
For Cb = 40pF, max is about 15~20k
NOTES:
1. IRQ & FOUT and EVDET Inactive.
2. LPMODE = 0 (default).
3. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
4. Typical values are for T = 25°C and 3.3V supply voltage.
5. VSUP=VDD if in VDD Mode, VSUP=VBAT if in VBAT Mode.
4
FN6109.1
September 27, 2005
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