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ISL12082IB8Z-T View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12082IB8Z-T I2C-Bus™ Real Time Clock with Two Interrupts, Alarm, and Timer Intersil
Intersil Intersil
ISL12082IB8Z-T Datasheet PDF : 26 Pages
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ISL12082
Serial Interface Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
(Note 6) (Note 5) (Note 6) UNITS NOTES
Cpin
fSCL
tIN
SDA and SCL Pin Capacitance
SCL Frequency
TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V,
VOUT = 0V
Pulse Width Suppression Time at Any pulse narrower than the max spec is
SDA and SCL Inputs
suppressed
10
pF
7, 8
400
kHz
50
ns
tAA
tBUF
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of VDD, until
Data Valid
SDA exits the 30% to 70% of VDD window
Time the Bus Must Be Free Before SDA crossing 70% of VDD during a STOP
the Start of a New Transmission condition, to SDA crossing 70% of VDD
during the following START condition
1300
900
ns
ns
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VDD crossing
Measured at the 70% of VDD crossing
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
From SDA falling edge crossing 30% of VDD
to SCL falling edge crossing 70% of VDD
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
From SCL falling edge crossing 30% of VDD
to SDA entering the 30% to 70% of VDD
window
1300
600
600
600
100
0
ns
ns
ns
ns
ns
900
ns
tSU:STO STOP Condition Setup Time
From SCL rising edge crossing 70% of VDD, 600
ns
to SDA rising edge crossing 30% of VDD
tHD:STO STOP Condition Hold Time
From SDA rising edge to SCL falling edge
600
ns
Both crossing 70% of VDD
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VDD,
0
ns
until SDA enters the 30% to 70% of VDD
window
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1 x Cb
300
ns
7, 8
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
300
ns
7, 8
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
7, 8
Rpu SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by tR and tF
1
For Cb = 400pF, max is about 2kΩ to ~2.5kΩ
For Cb = 40pF, max is about 15kΩ to ~20kΩ
kΩ
7, 8
NOTES:
2. IRQ and fOUT Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
5. Typical values are for T = +25°C and 3.3V supply voltage.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
7. Limits should be considered typical and are not production tested.
8. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate
specification.
9. Parameters are for 10 Ld MSOP package only.
5
FN6731.3
November 24, 2008
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