ISL12082IB8Z View Datasheet(PDF) - Intersil
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ISL12082IB8Z Datasheet PDF : 26 Pages
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ISL12082
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
Periodic Interrupt Mode:
• Single Event Mode is enabled by setting the ALME bit to
“1”, the IM bit to “0”, and IRQ1E bit to “1” and/or IRQ2E bit
to “0”. This mode permits a one-time match between the
alarm registers and the RTC registers. Once this match
occurs, the ALM status bit is set to “1” and the IRQ1/fOUT
and/or IRQ2 output will be pulled low and will remain low
until the ALM status bit is reset to “0”. This can be done
manually or by using the auto-reset feature.
• Periodic Interrupt Mode is enabled by setting the ALME
bit to “1”, the IM bit to “1”, and IRQ1E bit to “1” and/or
IRQ2E bit to “0”. The IRQ1/fOUT and/or IRQ2 output will
now be pulsed each time an alarm occurs. This means
that once the interrupt mode alarm is set, it will continue to
alarm for each occurring match of the alarm and present
time. This mode is convenient for hourly or daily hardware
interrupts in microcontroller applications such as security
cameras or utility meter reading.
To clear an alarm, the ALM status bit must be set to “0” with
a write. Note that if the ARST bit is set to “1” (address 07h,
Bit 7), the ALM bit will automatically be cleared when the
status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm registers as follows:
ALARM
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
SCA 0 0 0 0 0 0 0 0 00h Seconds disabled
MNA
1 0 1 1 0 0 0 0 B0h Minutes set to 30,
enabled
HRA
1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
DTA 1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
MOA
1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
DWA
0 0 0 0 0 0 0 0 00h Day of week
disabled
B. Set the ALME bit as follows:
CONTROL
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
INT
0 1 x x 0 0 0 0 x0h Enable Alarm
NOTE: x indicate other control bits
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ1/fOUT and
IRQ2 output low if IRQ1E bit is set to “1” and IRQ2E bit is set
to “0”.
Example 2 – Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30s.
A. Set alarm registers as follows:
ALARM
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
SCA
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA 0 0 0 0 0 0 0 0 00h Minutes disabled
HRA 0 0 0 0 0 0 0 0 00h Hours disabled
DTA 0 0 0 0 0 0 0 0 00h Date disabled
MOA 0 0 0 0 0 0 0 0 00h Month disabled
DWA 0 0 0 0 0 0 0 0 00h Day of week disabled
B. Set the Interrupt register as follows:
CONTROL
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
INT 1 1 x x 0 0 0 0 x0h Enable Alarm and Int
Mode
NOTE: x indicate other control bits
Once the registers are set, the following waveform will be
seen at IRQ:
RTC AND ALARM REGISTERS ARE BOTH 30s
60s
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
Timer Control Register (TMRC) [Address 09h]
TABLE 9. TIMER CONTROL REGISTER (TMRC)
ADDR 7
6
5
4 32 1
0
09h
TIM TMRE TMOD1 TMOD0 0 0 TCLK1 TCLK0
Default 0
0
0
0 00 0
0
TIMER CLOCK FREQUENCY SELECTION BITS
(TCLK <1:0>)
For detailed timer operation, please refer to “TIMER
COUNTER OPERATION” on page 17.
These bits select the Timer/Watchdog clock frequency for
the Timer Counter Register (TCNT, address 13h) and the
internal Sub-Timer Counter Register (TSCNT). When the
15
FN6731.3
November 24, 2008
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