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ISL1208IB8-TK View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL1208IB8-TK I2C® Real Time Clock/Calendar Intersil
Intersil Intersil
ISL1208IB8-TK Datasheet PDF : 24 Pages
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ISL1208
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
NOTES (Note 9) (Note 8) (Note 9) UNITS
VIH
SDA and SCL Input Buffer HIGH
Voltage
Hysteresis SDA and SCL Input Buffer
Hysteresis
VOL SDA Output Buffer LOW Voltage,
Sinking 3mA
0.7 x
VDD
0.05 x
VDD
0
VDD +
V
0.3
V
0.4
V
CPIN
fSCL
tIN
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
tDH
tR
SDA and SCL Pin Capacitance
SCL Frequency
TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V,
VOUT = 0V
Pulse width Suppression Time at Any pulse narrower than the max spec is
SDA and SCL Inputs
suppressed.
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must Be Free Before
the Start of a New Transmission
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window.
SDA crossing 70% of VDD during a STOP
condition, to SDA crossing 70% of VDD
during the following START condition.
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
Measured at the 30% of VDD crossing.
Measured at the 70% of VDD crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD.
From SDA falling edge crossing 30% of VDD
to SCL falling edge crossing 70% of VDD.
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
From SCL falling edge crossing 30% of VDD
to SDA entering the 30% to 70% of VDD
window.
STOP Condition Setup Time
STOP Condition Hold Time
Output Data Hold Time
From SCL rising edge crossing 70% of VDD,
to SDA rising edge crossing 30% of VDD.
From SDA rising edge to SCL falling edge.
Both crossing 70% of VDD.
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window.
SDA and SCL Rise Time
From 30% to 70% of VDD
10, 11
10, 11
1300
1300
600
600
600
100
20
600
600
0
20 +
0.1 x Cb
10
pF
400
kHz
50
ns
900
ns
ns
ns
ns
ns
ns
ns
900
ns
ns
ns
ns
300
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
10, 11 20 +
0.1 x Cb
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10, 11
10
Rpu SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by tR and tF.
10, 11
1
For Cb = 400pF, max is about 2kΩ to~2.5kΩ.
For Cb = 40pF, max is about 15kΩ to ~20kΩ
300
ns
400
pF
kΩ
NOTES:
5. IRQ and FOUT Inactive.
6. LPMODE = 0 (default).
7. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
8. Typical values are for T = +25°C and 3.3V supply voltage.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Parameter is not 100% tested.
11. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
5
FN8085.8
September 12, 2008
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