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ISL1208IU8Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL1208IU8Z I2C® Real Time Clock/Calendar Intersil
Intersil Intersil
ISL1208IU8Z Datasheet PDF : 24 Pages
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A system to implement temperature compensation would
consist of the ISL1208, a temperature sensor, and a
microcontroller. These devices may already be in the system
so the function will just be a matter of implementing software
and performing some calculations. Fairly accurate
temperature compensation can be implemented just by
using the crystal manufacturer’s specifications for the
turnover temperature T0 and the drift coefficient (β). The
formula for calculating the oscillator adjustment necessary is
Equation 3:
Adjustment(ppm) = (T – T0)2 ∗β
(EQ. 3)
Once the temperature curve for a crystal is established, then
the designer should decide at what discrete temperatures
the compensation will change. Since drift is higher at
extreme temperatures, the compensation may not be
needed until the temperature is greater than +20°C from T0.
A sample curve of the ATR setting vs Frequency Adjustment
for the ISL1208 and a typical RTC crystal is given in
Figure 18. This curve may vary with different crystals, so it is
good practice to evaluate a given crystal in an ISL1208
circuit before establishing the adjustment values.
5 10 15 20 25 30 35 40 45 50 55 60
This curve is then used to figure what ATR and DTR settings
are used for compensation. The results would be placed in a
lookup table for the microcontroller to access.
Note that the ATR register affects the FOUT frequency
directly. Also, the DTR setting will affect the FOUT frequency
for all but the 32.768Khz setting, due to the clock correction
in the divider chain.
Layout Considerations
The crystal input at X1 has a very high impedance, and
oscillator circuits operating at low frequencies such as
32.768kHz are known to pick up noise very easily if layout
precautions are not followed. Most instances of erratic
clocking or large accuracy errors can be traced to the
susceptibility of the oscillator circuit to interference from
adjacent high speed clock or data lines. Careful layout of the
RTC circuit will avoid noise pickup and insure accurate
Figure 19 shows a suggested layout for the ISL1208 device
using a surface mount crystal. Two main precautions should
be followed:
1. Do not run the serial bus lines or any high speed logic
lines in the vicinity of the crystal. These logic level lines
can induce noise in the oscillator circuit to cause
2. Add a ground trace around the crystal with one end
terminated at the chip ground. This will provide
termination for emitted noise in the vicinity of the RTC
In addition, it is a good idea to avoid a ground plane under
the X1 and X2 pins and the crystal, as this will affect the load
capacitance and therefore the oscillator accuracy of the
circuit. If the IRQ/FOUT pin is used as a clock, it should be
routed away from the RTC device as well. The traces for the
VBAT and VCC pins can be treated as a ground, and should
be routed around the crystal.
Battery Backup Considerations
The ISL1208 device provides a VBAT pin which is used for a
battery backup input. The battery voltage can vary from 1.8V
up to 5.5V, independent of the VDD supply voltage. An
internal switch automatically connects the VBAT supply to
the to the internal power node when VDD power goes away,
and switches back to VDD when power returns.
Since this battery switch draws power from the battery, it is
very low power and not very fast. If the VDD drops too
quickly to 0V, there is not enough time for the switch to
connect the VBAT source to the internal power node, and the
SRAM contents can be lost or corrupted. It is a good idea to
keep power-down ramps longer than 50us to insure data
Battery drain can be minimized by using the LPMODE
option. Since normally the VBAT and VDD need to be
monitored in order to switch at the lower voltage, two
comparator function are needed during battery backup.
LPMODE shuts off one of the comparators and just
compares VDD to VBAT to activate switchover. This saves
about 500nA of VBAT current at 3.0V. Do not use LPMODE
when VBAT ≥ VDD - 0.2V, to avoid permanently placing the
device in battery backup mode.
September 12, 2008
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