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ISL1208IU8Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL1208IU8Z I2C® Real Time Clock/Calendar Intersil
Intersil Intersil
ISL1208IU8Z Datasheet PDF : 24 Pages
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ISL1208
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These
bits are “1101111”. Slave bits “1101” access the register.
Slave bits “111” specify the device select bits.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(Refer to Figure 15).
After loading the entire Slave Address Byte from the SDA
bus, the ISL1208 compares the device identifier and device
select bits with “1101111”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up the internal
address counter is set to address 0h, so a current address
read of the CCR array starts at address 0h. When required,
as part of a random read, the master must supply the 1 Word
Address Bytes as shown in Figure 16.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. For a random read of the Clock/Control Registers,
the slave byte must be “1101111x” in both places.
1
1
0
1
11
1
R/W
SLAVE
ADDRESS BYTE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL1208 responds with an ACK. At this time, the I2C
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 16). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL1208 responds with an ACK. Then
the ISL1208 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (See Figure 16).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 13h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
SIGNALS
FROM THE
MASTER
S
T IDENTIFICATION
A
BYTE WITH
R
R/W = 0
T
ADDRESS
BYTE
S
T IDENTIFICATION
A BYTE WITH
R
R/W = 1
T
S
A
A
T
C
C
O
K
K
P
SIGNAL AT
SDA
11011110
A
SIGNALS FROM
C
THE SLAVE
K
11011111
A
A
C
C FIRST READ
K
K DATA BYTE
LAST READ
DATA BYTE
FIGURE 16. READ SEQUENCE
17
FN8085.8
September 12, 2008
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