ISL1208IU8 View Datasheet(PDF) - Intersil
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ISL1208IU8 Datasheet PDF : 24 Pages
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ISL1208
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM=”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm registers as follows:
ALARM
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
SCA 0 0 0 0 0 0 0 0 00h Seconds disabled
MNA
1 0 1 1 0 0 0 0 B0h Minutes set to 30,
enabled
HRA
1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
DTA 1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
MOA
1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
DWA
0 0 0 0 0 0 0 0 00h Day of week
disabled
B. Also the ALME bit must be set as follows:
CONTROL
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
INT
0 1 x x 0 0 0 0 x0h Enable Alarm
xx indicate other control bits
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ output low.
Example 2 – Pulsed interrupt once per minute (IM=”1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm registers as follows:
ALARM
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
SCA
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA 0 0 0 0 0 0 0 0 00h Minutes disabled
HRA 0 0 0 0 0 0 0 0 00h Hours disabled
DTA 0 0 0 0 0 0 0 0 00h Date disabled
MOA 0 0 0 0 0 0 0 0 00h Month disabled
DWA 0 0 0 0 0 0 0 0 00h Day of week disabled
B. Set the Interrupt register as follows:
CONTROL
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
INT 1 1 x x 0 0 0 0 x0h Enable Alarm and Int
Mode
xx indicate other control bits
Once the registers are set, the following waveform will be
seen at IRQ-:
RTC AND ALARM REGISTERS ARE BOTH “30”s
60s
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
User Registers
Addresses [12h to 13h]
These registers are 2 bytes of battery-backed user memory
storage.
I2C Serial Interface
The ISL1208 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is the master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL1208
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 12). On power-up of the ISL1208, the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL1208 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 12). A START condition is ignored during the
power-up sequence.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 12). A STOP condition at the end
of a read operation or at the end of a write operation to
memory only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
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FN8085.8
September 12, 2008
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