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ISL1208IU8Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL1208IU8Z I2CŪ Real Time Clock/Calendar Intersil
Intersil Intersil
ISL1208IU8Z Datasheet PDF : 24 Pages
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ISL1208
The effective series load capacitance is the combination of
CX1 and CX2 in Equation 2.:
CLOAD
=
----------------1------------------
⎛
⎝
-----1-----
CX1
+
C-----1X----2-⎠⎞
(EQ. 2)
CLOAD
=
⎛
⎝
1---6-----⋅---b---5----+-----8----⋅---b---4-----+----4----⋅---b----3----+----2-2----⋅---b---2----+----1-----⋅---b---1----+-----0---.-5----⋅----b---0----+----9--⎠⎞
p
F
For example, CLOAD (ATR = 00000) = 12.5pF, CLOAD (ATR =
100000) = 4.5pF, and CLOAD (ATR = 011111) = 20.25pF. The
entire range for the series combination of load capacitance
goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these
are typical values.
BATTERY MODE ATR SELECTION (BMATR <1:0>)
Since the accuracy of the crystal oscillator is dependent on
the VDD/VBAT operation, the ISL1208 provides the capability
to adjust the capacitance between VDD and VBAT when the
device switches between power sources.
BMATR1
0
0
1
1
BMATR0
0
1
0
1
DELTA
CAPACITANCE
(CBAT TO CVDD)
0pF
-0.5pF (≈ +2ppm)
+0.5pF (≈ -2ppm)
+1pF (≈ -4ppm)
DIGITAL TRIMMING REGISTER (DTR <2:0>)
The digital trimming bits DTR0, DTR1, and DTR2 adjust the
average number of counts per second and average the ppm
error to achieve better accuracy.
â€Ē DTR2 is a sign bit. DTR2 = “0” means frequency
compensation is >0. DTR2 = “1” means frequency
compensation is <0.
â€Ē DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -60ppm to +60ppm can be represented by
using these three bits (see Table 5).
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR2
DTR REGISTER
DTR1
DTR0
ESTIMATED
FREQUENCY
PPM
0
0
0
0 (default)
0
0
1
+20
0
1
0
+40
0
1
1
+60
1
0
0
0
1
0
1
-20
1
1
0
-40
1
1
1
-60
Alarm Registers
Addresses [0Ch to 11h]
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
â€Ē Single Event Mode is enabled by setting the ALME bit to
“1”, the IM bit to “0”, and disabling the frequency output.
This mode permits a one-time match between the alarm
registers and the RTC registers. Once this match occurs,
the ALM bit is set to “1” and the IRQ output will be pulled
low and will remain low until the ALM bit is reset. This can
be done manually or by using the auto-reset feature.
â€Ē Interrupt Mode is enabled by setting the ALME bit to “1”,
the IM bit to “1”, and disabling the frequency output. The
IRQ output will now be pulsed each time an alarm occurs.
This means that once the interrupt mode alarm is set, it
will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for
hourly or daily hardware interrupts in microcontroller
applications such as security cameras or utility meter
reading.
To clear an alarm, the ALM bit in the status register must be
set to “0” with a write. Note that if the ARST bit is set to 1
(address 07h, bit 7), the ALM bit will automatically be cleared
when the status register is read.
14
FN8085.8
September 12, 2008
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