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ISL12058IUZ View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12058IUZ Low Cost and Low Power I2C-Bus™ Real Time Clock/Calendar Intersil
Intersil Intersil
ISL12058IUZ Datasheet PDF : 19 Pages
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ISL12058
REG
ADDR. SECTION NAME
00h
SC
01h
MN
02h
HR
03h
RTC
DT
04h
MO
05h
YR
06h
DW
07h Status
SR
08h Control
INT
09h
Not Used
0Ah
Not Used
0Bh
Not Used
0Ch
A1SC
0Dh
A1MN
0Eh
A1HR
Alarm1
0Fh
A1DT
10h
A1MO
11h
A1DW
12h
A2MN
13h
A2HR
Alarm2
14h
A2DW/DT
7
0
0
MIL
0
0
YR23
0
ARST
0
0
0
0
A1M1
A1M2
A1M3
A1M4
A1M5
A1M6
A2M2
A2M3
A2M4
TABLE 1. REGISTER MEMORY MAP
BIT
REG
6
5
4
3
2
1
0
RANGE DEFAULT
SC22
SC21
SC20
SC13
SC12
SC11
SC10 0 to 59
00h
MN22
MN21
MN20 MN13
MN12
MN11
MN10 0 to 59
00h
0
HR21
HR20
HR13
HR12
HR11
HR10 0 to 23
00h
0
DT21
DT20
DT13
DT12
DT11
DT10 1 to 31
01h
0
0
MO20 MO13 MO12 MO11
MO10 1 to 12
01h
YR22
YR21
YR20
YR13
YR12
YR11
YR10 0 to 99
00h
0
0
0
0
DW12 DW11 DW10 0 to 6
00h
XSTOP
0
WRTC
OSF
A1F
A2F
PF
N/A
09h
ALM1E ALM2E FO1
FO0
IRQE
0
A1E
N/A
18h
0
0
0
0
0
0
0
N/A
00h
0
0
0
0
0
0
0
N/A
00h
0
0
0
0
0
0
0
N/A
00h
A1SC22 A1SC21 A1SC20 A1SC13 A1SC12 A1SC11 A1SC10 00 to 59 00h
A1MN22 A1MN21 A1MN20 A1MN13 A1MN12 A1MN11 A1MN10 00 to 59 00h
A1MIL A1HR21 A1HR20 A1HR13 A1HR12 A1HR11 A1HR10 0 to 23
00h
0
A1DT21 A1DT20 A1DT13 A1DT12 A1DT11 A1DT10 1 to 31
00h
0
0
A1MO20 A1MO13 A1MO12 A1MO11 A1MO10 1 to 12
00h
0
0
0
0
A1DW12 A1DW11 A1DW10 0 to 6
00h
A2MN22 A2MN21 A2MN20 A2MN13 A2MN12 A2MN11 A2MN10 00 to 59 00h
A2MIL A2HR21 A2HR20 A2HR13 A2HR12 A2HR11 A2HR10 0 to 23
00h
A2DW/DT A2DT21 A2DT20 A2DT13 A2DT12 A2DT11 A2DT10 1 to 31
00h
A2DW12 A2DW11 A2DW10 0 to 6
00h
Address 09h to 0Bh and 15h to 1Fh are not used. Reads or
writes to these registers will not affect operation of the
device but should be avoided.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC registers, the read instruction
latches all clock registers into a buffer, so an update of the
clock does not change the time being read. A sequential
read will not result in the output of data from the memory
array. At the end of a read, the master supplies a stop
condition to end the operation and free the bus. After a read
or write instruction, the address remains at the previous
address +1 so the user can execute a current address read
and continue reading the next register.
.
Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR,DW, DT, MO, YR)
These registers depict BCD representations of the time. As
such, SC (Seconds, address 00h) and MN (Minutes,
address 01h) range from 0 to 59, HR (Hour, address 02h)
can either be a 12-hour or 24-hour mode, DT (Date, address
03h) is 1 to 31, MO (Month, address 04h) is 1 to 12, YR
(Year, address 06h) is 0 to 99, and DW (Day of the Week,
address 06h) is 0 to 6.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
9
FN6756.0
June 15, 2009
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