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ISL12058IUZ View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12058IUZ Low Cost and Low Power I2C-Bus™ Real Time Clock/Calendar Intersil
Intersil Intersil
ISL12058IUZ Datasheet PDF : 19 Pages
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ISL12058
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 7) (Note 8) UNITS NOTES
tIN
Pulse width Suppression Time at Any pulse narrower than the max
SDA and SCL Inputs
spec is suppressed
50
ns
tAA
tBUF
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing
70% of VDD during the following
START condition
1300
900
ns
11
ns
tLOW Clock LOW Time
Measured at the 30% of VDD
1300
ns
crossing
tHIGH Clock HIGH Time
Measured at the 70% of VDD
600
ns
crossing
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
tDH
tR
tF
Cb
START Condition Setup Time
SCL rising edge to SDA falling
600
edge. Both crossing 70% of VDD
START Condition Hold Time
From SDA falling edge crossing
600
30% of VDD to SCL falling edge
crossing 70% of VDD
Input Data Setup Time
From SDA exiting the 30% to 70%
100
of VDD window, to SCL rising edge
crossing 30% of VDD
Input Data Hold Time
From SCL falling edge crossing
0
30% of VDD to SDA entering the
30% to 70% of VDD window
STOP Condition Setup Time
From SCL rising edge crossing
600
70% of VDD, to SDA rising edge
crossing 30% of VDD
STOP Condition Hold Time
From SDA rising edge to SCL
600
falling edge. Both crossing 70% of
VDD
Output Data Hold Time
From SCL falling edge crossing
0
30% of VDD, until SDA enters the
30% to 70% of VDD window
SDA and SCL Rise Time
From 30% to 70% of VDD
20 + 0.1 x Cb
SDA and SCL Fall Time
From 70% to 30% of VDD
20 + 0.1 x Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
ns
ns
ns
900
ns
ns
ns
ns
300
ns 9, 10
300
ns 9, 10, 11
400
pF 9, 10
Rpu SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by tR and
1
tF.
For Cb = 400pF, max is about
2kΩ to~2.5kΩ.
For Cb = 40pF, max is about 15kΩ
to ~20kΩ
kΩ 9, 10
NOTES:
6. IRQ/FOUT inactive.
7. Typical values are for T = +25°C and 3.3V supply voltage.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
9. Limits should be considered typical and are not production tested.
10. These are I2C specific parameters and are not production tested, however, they are used to set conditions for testing devices to
validate specification.
11. Parts will work with SDA pull-up voltage above the VPULLUP limit but the tAA and tFin the I2C parameters are not guaranteed.
12. Specified at +25°C.
5
FN6756.0
June 15, 2009
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