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ISL12058IUZ View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12058IUZ Low Cost and Low Power I2C-Bus? Real Time Clock/Calendar Intersil
Intersil Intersil
ISL12058IUZ Datasheet PDF : 19 Pages
First Prev 11 12 13 14 15 16 17 18 19
ISL12058
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE ISL12058
R/W BIT = “0”
S
T
A IDENTIFICATION
R
BYTE
T
ADDRESS
BYTE
11011110
A
C
K
FIRST DATA
BYTE
A
A
C
C
K
K
S
LAST DATA
T
BYTE
O
P
A
A
C
C
K
K
FIGURE 9. SEQUENTIAL BYTE WRITE SEQUENCE
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs of the Slave Address Byte are
the device identifier bits, and the device identifier bits are
“1101111”.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(refer to Figure 10).
After loading the entire Slave Address Byte from the SDA
bus, the ISL12058 compares the device identifier bits with
“1101111”. Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Address Byte is a 1 byte register
address. The register address is supplied by the master
device. On power-up, the internal address counter is set to
address 0h, so a current address read of the RTC array
starts at address 0h. When required, as part of a random
read, the master must supply the 1 Word Address Bytes as
shown in Figure 11.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. For a random read of the Clock/Control Registers,
the slave byte must be “1101111x” in both places.
1
1
0
1
11
1
R/W
SLAVE
ADDRESS BYTE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12058 responds with an ACK. At this time, the I2C
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 11). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL12058 responds with an ACK. Then
the ISL12058 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 11).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer’s initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 1Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
A7 A6 A5 A4 A3 A2 A1 A0 REGISTER
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
14
FN6756.0
June 15, 2009
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