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ISL12058IUZ View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12058IUZ Low Cost and Low Power I2C-Bus™ Real Time Clock/Calendar Intersil
Intersil Intersil
ISL12058IUZ Datasheet PDF : 19 Pages
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ISL12058
ALARM1
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
A1SC 0 0 0 0 0 0 0 0 00h Seconds disabled
A1MN 1 0 1 1 0 0 0 0 B0h Minutes set to 30,
enabled
A1HR 1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
A1DT
1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
A1MO 1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
A1DW 0 0 0 0 0 0 0 0 00h Day of week
disabled
B. Also the ALME bit must be set as follows:
CONTROL
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
INT
0 1 x x x 1 0 1 45h Enable Alarm1,
and Alarm1
Interrupt to
IRQ/FOUT
xx indicate other control bits and these bit can be set to 0 or
1.
After these registers are set, the Alarm1 interrupt will be
generated when the RTC advances to exactly 11:30am on
January 1 (after seconds changes from 59 to 00) by setting
the A1F bit in the status register to “1” and also bringing the
IRQ/FOUT output low.
Alarm2 Registers
Addresses [Address 12h to 14h]
The Alarm2 register bytes are set up identical to the RTC
register bytes except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (minutes, hour, and date/day) are used to
make the comparison. Note that there are no alarm bytes for
second, month and year. When all the enable bits are set to
“0” with ALM2E set to “1”, the Alarm2 will triggered once a
minute when second hits “00”.
The Alarm2 function works as a comparison between the
Alarm2 registers and the RTC registers. As the RTC
advances, the Alarm2 will be triggered once a match occurs
between the Alarm2 registers and the RTC registers. Any
one Alarm2 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm2, the A2F status bit can be set to “0” with a
write or use the ARST bit auto reset function.
TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS
SELECTION
A2DW/DT A2M2 A2M3 A2M4
ALARM2 Interrupt
0
0
0
0 Every Minute (Second=00)
0
1
0
0
Match Minute
0
0
1
0
Match Hour
0
0
0
1
Match Date
1
0
0
1
Match Day
0
1
1
0
Match Minute and Hour
0
1
0
1
Match Minute and Date
0
0
1
1
Match Hour and Date
0
1
1
1 Match Minute, Hour, and Date
1
1
1
0
Match Minute and Hour
1
1
0
1
Match Minute and Day
1
0
1
1
Match Hour and Day
1
1
1
1 Match Minute, Hour, and Day
Following is example of Alarm2 Interrupt.
Example – A single alarm will occur on every Monday at
20:00 military time (Monday is when DW = 1).
A. Set Alarm registers as follows:
ALARM2
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
A2MN 0 0 0 0 0 0 0 0 00h Minutes disabled
A2HR 1 1 1 0 0 0 0 0 E0h Hours set to 20,
enabled
A2DW/DT 1 1 0 0 0 0 0 1 C1h Day set to Monday,
enabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 20:00 on Monday (after minutes
changes from 59 to 00) by setting the A2F bit in the status
register to “1”.
I2C Serial Interface
The ISL12058 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12058 operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
12
FN6756.0
June 15, 2009
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