ISL12029IV27Z View Datasheet(PDF) - Intersil

Part Name

Description

View to exact match

ISL12029IV27Z

Real Time Clock/Calendar with I2C Bus™ and EEPROM

Intersil 

ISL12029, ISL12029A

Watchdog Timer/Low Voltage Reset Parameters

SYMBOL

PARAMETER

CONDITIONS

tRPD

tPURST

VRVALID

VDD Detect to RESET LOW

Power-Up Reset Time-Out Delay

Minimum VDD for Valid RESET

Output

VRESET ISL12029-4.5A Reset Voltage Level

ISL12029 Reset Voltage Level

ISL12029-3 Reset Voltage Level

ISL12029-2.7A Reset Voltage Level

ISL12029-2.7 Reset Voltage Level

tWDO Watchdog Timer Period

32.768kHz crystal between X1

and X2

tRST

Watchdog Timer Reset Time-Out

Delay

32.768kHz crystal between X1

and X2

tRSP I2C Interface Minimum Restart Time

EEPROM SPECIFICATIONS

EEPROM Endurance

EEPROM Retention

Temperature ≤ +75°C

MIN

TYP

(Note 16) (Note 11)

500

100

250

1.0

MAX

(Note 16)

400

4.59

4.64

4.69

4.33

4.38

4.43

3.04

3.09

3.14

2.87

2.92

2.97

2.58

2.63

2.68

1.70

1.75

1.801

725

750

775

225

250

275

225

250

275

1.2

>2,000,000

50

UNITS

ns

ms

V

V

V

V

V

V

s

ms

ms

ms

µs

Cycles

Years

NOTES

13

Serial Interface (I2C) Specifications - DC/AC Characteristics

SYMBOL

PARAMETER

CONDITIONS

MIN

(Note 16) TYP

VIL

SDA, and SCL Input Buffer LOW SBIB = 1 (Under VDD mode)

-0.3

Voltage

VIH

SDA, and SCL Input Buffer HIGH SBIB = 1 (Under VDD mode)

Voltage

0.7 x VDD

Hysteresis SDA and SCL Input Buffer

Hysteresis

SBIB = 1 (Under VDD mode)

0.05 x VDD

VOL SDA Output Buffer LOW Voltage

ILI

Input Leakage Current on SCL

ILO

I/O Leakage Current on SDA

TIMING CHARACTERISTICS

IOL = 4mA

VIN = 5.5V

VIN = 5.5V

0

0.1

0.1

fSCL SCL Frequency

tIN

Pulse Width Suppression Time at Any pulse narrower than the max

SDA and SCL Inputs

spec is suppressed.

tAA

tBUF

SCL Falling Edge to SDA Output

Data Valid

SCL falling edge crossing 30% of

VDD, until SDA exits the 30% to

70% of VDD window.

Time the Bus Must be Free Before

the Start of a New Transmission

SDA crossing 70% of VDD during

a STOP condition, to SDA

crossing 70% of VDD during the

following START condition.

1300

tLOW Clock LOW Time

Measured at the 30% of VDD

crossing.

1300

MAX

(Note 16)

0.3 x VDD

UNITS

V

NOTES

VDD + 0.3

V

V

0.4

V

10

µA

10

µA

400

kHz

50

ns

900

ns

ns

ns

5

FN6206.10

December 16, 2010

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