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ISL12029IV27AZ View Datasheet(PDF) - Intersil

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ISL12029IV27AZ Datasheet PDF : 29 Pages
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ISL12029, ISL12029A
EXAMPLE 2
Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm 0 registers as follows:
BIT
ALARM0
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
SCA0
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled
HRA0 0 0 0 0 0 0 0 0 00h Hours disabled
DTA0 0 0 0 0 0 0 0 0 00h Date disabled
MOA0 0 0 0 0 0 0 0 0 00h Month disabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled
B. Set the Interrupt register as follows:
BIT
CONTROL
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
INT 1 0 1 x x 0 0 0 x0h Enable Alarm and Int
Mode
XX indicate other control bits
Once the registers are set, the following waveform will be
seen at IRQ/FOUT:
RTC AND ALARM REGISTERS ARE BOTH 30s
60s
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
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27
FN6206.10
December 16, 2010
 

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