datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ISL12029IV27Z View Datasheet(PDF) - Intersil

Part Name
Description
View to exact match
ISL12029IV27Z Datasheet PDF : 29 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
ISL12029, ISL12029A
OPTION 2 - LEGACY POWER CONTROL MODE
(DEFAULT FOR ISL12029)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from VDD to VBAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the VBAT voltage is
higher than VDD, then the device will enter battery backup and
unless the battery is disconnected or the voltage decreases,
the device will no longer operate from VDD. If that is the
situation on initial power-up, then I2C communication may not
be possible. For these applications, the ISL12029A should be
used.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1.”
• Normal Mode (VDD) to Battery Backup Mode (VBAT)
To transition from the VDD to VBAT mode, the following
conditions must be met:
VDD < VBAT - VBATHYS
• Battery Backup Mode (VBAT) to Normal Mode (VDD)
The device will switch from the VBAT to VDD mode when the
following condition occurs:
VDD > VBAT +VBATHYS
The Legacy Mode power control conditions are illustrated in
Figure 15.
VBAT
VDD
OFF
VOLTAGE
ON
IN
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
Power-on Reset
Application of power to the ISL12029 activates a Power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
- It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VDD exceeds the device VRESET threshold value for
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
NOTE: If the VBAT voltage drops below the data sheet
minimum of 1.8V and the VDD power cycles to 0V then back
to VDD voltage, then the RESET output may stay low and the
I2C communications will not operate. The VBAT and VDD
power will need to be cycled to 0V together to allow normal
operation again.
Watchdog Timer Operation
The Watchdog timer time-out period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set to
3 different time-out periods or off. When the Watchdog timer
is set to off, the Watchdog circuit is configured for low power
operation (see Table 8).
TABLE 8. WATCHDOG TIMER OPERATION
WD1
WD0
DURATION
1
1
disabled
1
0
250ms
0
1
750ms
0
0
1.75s
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the Watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the Watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh Watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode (see Figure 3).
In battery mode, the Watchdog timer function is disabled.
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the VDD line versus a preset threshold
voltage (VRESET), then generates a RESET pulse if it is
below VRESET. The reset pulse will time-out 250ms after the
VDD line rises above VRESET. If the VDD remains below
VRESET, then the RESET output will remain asserted low.
Power-up and power-down waveforms are shown in
Figure 4. The LVR circuit is to be designed so the RESET
signal is valid down to VDD = 1.0V.
When the LVR signal is active, unless the part has been
switched into the battery mode, the completion of an
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
17
FN6206.10
December 16, 2010
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]