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ISL12028IV30AZ View Datasheet(PDF) - Intersil

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ISL12028IV30AZ Datasheet PDF : 29 Pages
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ISL12028, ISL12028A
Control Registers (Non-Volatile)
The Control Bits and Registers described in the following are
non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
TABLE 3. BLOCK PROTECT PARTITIONS
PROTECTED ADDRESSES
ISL12028
ARRAY LOCK
000
None (Default)
None
001
010
011
100
101
110
111
180h – 1FFh
100h – 1FFh
000h – 1FFh
000h – 03Fh
000h – 07Fh
000h – 0FFh
000h – 1FFh
Upper 1/4
Upper 1/2
Full Array
First 4 Pages
First 8 Pages
First 16 Pages
Full Array
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits; Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output (IRQ/
FOUT). The interrupts are enabled when either the AL1E or
AL0E or both bits are set to ‘1’ and both the FO1 and FO0
bits are set to 0 (FOUT disabled).
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/FOUT output will now be pulsed each time an
alarm occurs. This means that once the interrupt mode
alarm is set, it will continue to alarm for each occurring
match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
In the case that both Alarm 0 and Alarm 1 are enabled, the
IRQ/FOUT pin will be pulsed each time either alarm matches
the RTC (both alarms can provide hardware interrupt). If the
IM bit is also set to "1", the IRQ/FOUT will be pulsed for each
of the alarms as well.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the IRQ/
FOUT output pin. Table 4 shows the selection bits for this
output. When using this function, the Alarm output function is
disabled.
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
FO1 FO0
OUTPUT FREQUENCY
0
0
0
1
Alarm output (FOUT disabled)
32.768kHz
1
0
1
1
4096Hz
1Hz
Oscillator Compensation Registers
There are two trimming options.
- ATR. Analog Trimming Register
- DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110 ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
X1
CX1
X2
CX2
CRYSTAL
OSCILLATOR
FIGURE 12. DIAGRAM OF ATR
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
and X2 pins to ground (see Figure 12). The value of CX1 and
CX2 is given by Equation 1:
CX = (16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9)pF
(EQ. 1)
13
FN8233.8
August 9, 2010
 

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