|ISL12024IVZ||Real-Time Clock/Calendar with Embedded Unique ID|
|ISL12024IVZ Datasheet PDF : 25 Pages |
AC Electrical Specifications (Continued)
(Note 12) TYP (Note 12) UNITS NOTES
Cpin SDA and SCL Pin Capacitance
tWC Non-Volatile Write Cycle Time
SDA and SCL Rise Time
From 30% to 70% of VDD (Note 11)
0.1 x Cb
SDA and SCL Fall Time
From 70% to 30% of VDD (Note 11)
0.1 x Cb
Cb Capacitive Loading of SDA or Total on-chip and off-chip. (Note 11)
RPU SDA and SCL Bus Pull-up
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2kΩ~2.5kΩ.
For Cb = 40pF, max is about 15kΩ~20kΩ
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT ≥1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end
of Write sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
11. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Write Cycle Timing
8TH BIT OF LAST BYTE
August 18, 2008
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