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ISL12020M View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12020M Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving Intersil
Intersil Intersil
ISL12020M Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ISL12020M
DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise
stated. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
(Note 8) (Note 9) (Note 8) UNITS NOTES
IRQ/FOUT (OPEN DRAIN OUTPUT)
VOL Output Low Voltage
VDD = 5V, IOL = 3mA
VDD = 2.7V, IOL = 1mA
0.4
V
0.4
V
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
(Note 8) (Note 9) (Note 8) UNITS NOTES
VDDSR-
VDD Negative Slew rate
10
V/ms
14
I2C Interface Specifications
Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise
specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 8) (Note 9) (Note 8) UNITS NOTES
VIL
SDA and SCL Input Buffer
LOW Voltage
VIH
SDA and SCL Input Buffer
HIGH Voltage
-0.3
0.7 x VDD
0.3 x
V
VDD
VDD +
V
0.3
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V
15, 16
VOL
SDA Output Buffer LOW
VDD = 5V, IOL = 3mA
0
Voltage, Sinking 3mA
0.02
0.4
V
CPIN
fSCL
tIN
SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V,
VOUT = 0V
SCL Frequency
Pulse Width Suppression
Any pulse narrower than
Time at SDA and SCL Inputs the max spec is
suppressed.
10
pF
15, 16
400
kHz
50
ns
tAA
tBUF
SCL Falling Edge to SDA
Output Data Valid
Time the Bus Must be Free
Before the Start of a New
Transmission
SCL falling edge
crossing 30% of VDD,
until SDA exits the 30%
to 70% of VDD window.
SDA crossing 70% of
VDD during a STOP
condition, to SDA
crossing 70% of VDD
during the following
START condition.
1300
900
ns
ns
tLOW
Clock LOW Time
Measured at the 30% of 1300
ns
VDD crossing.
tHIGH
Clock HIGH Time
Measured at the 70% of
600
ns
VDD crossing.
tSU:STA
START Condition Setup Time SCL rising edge to SDA
600
ns
falling edge. Both
crossing 70% of VDD.
6
FN6667.4
February 11, 2010
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